TMS320C6713B Floating-Point Digital Signal Processor (Rev. A)

SPRS294A − OCTOBER 2005 − REVISED NOVEMBER 2005
PLL and PLL controller (continued)
The PLL Reset Time is the amount of wait time needed when resetting the PLL (writing PLLRST=1), in order
for the PLL to properly reset, before bringing the PLL out of reset (writing PLLRST = 0). For the PLL Reset Time
value, see Table 33. The PLL Lock Time is the amount of time from when PLLRST = 0 with PLLEN = 0 (PLL
out of reset, but still bypassed) to when the PLLEN bit can be safely changed to “1” (switching from bypass to
the PLL path), see Table 33 and Figure 15.
Under some operating conditions, the maximum PLL Lock Time may vary from the specified typical value. For
the PLL Lock Time values, see Table 33.
Table 33. PLL Lock and Reset Times
MIN TYP MAX UNIT
PLL Lock Time 75 187.5 µs
PLL Reset Time 125 ns
Table 34 shows the device’s CLKOUT signals, how they are derived and by what register control bits, and what
is the default settings. For more details on the PLL, see the PLL and Clock Generator Logic diagram (Figure 15).
CLOCK OUTPUT
SIGNAL NAME
CLKOUT2
Table 34. CLKOUT Signals, Default Settings, and Control
DEFAULT SETTING
(ENABLED or DISABLED)
ON (ENABLED)
CONTROL
BIT(s) (Register)
D2EN = 1 (PLLDIV2.[15])
CK2EN = 1 (EMIF GBLCTL.[3])
DESCRIPTION
SYSCLK2 selected [default]
CLKOUT3 ON (ENABLED) OD1EN = 1 (OSCDIV1.[15]) Derived from CLKIN
SYSCLK3 selected [default].
ECLKOUT
ON (ENABLED);
derived from SYSCLK3
EKSRC = 0 (DEVCFG.[4])
EKEN = 1 (EMIF GBLCTL.[5])
To select ECLKIN source:
EKSRC = 1 (DEVCFG.[4]) and
EKEN = 1 (EMIF GBLCTL.[5])
The input clock (CLKIN) is directly available to the McASP modules as AUXCLK for use as an internal
high-frequency clock source. The input clock (CLKIN) may also be divided down by a programmable divider
OSCDIV1 (/1, /2, /3, ..., /32) and output on the CLKOUT3 pin for other use in the system.
Figure 15 shows that the input clock source may be divided down by divider PLLDIV0 (/1, /2, ..., /32) and then
multiplied up by a factor of x4, x5, x6, and so on, up to x25.
Either the input clock (PLLEN = 0) or the PLL output (PLLEN = 1) then serves as the high-frequency reference
clock for the rest of the DSP system. The DSP core clock, the peripheral bus clock, and the EMIF clock may
be divided down from this high-frequency clock (each with a unique divider) . For example, with a 30 MHz input
if the PLL output is configured for 450 MHz, the DSP core may be operated at 225 MHz (/2) while the EMIF may
be configured to operate at a rate of 75 MHz (/6). Note that there is a specific minimum and maximum reference
clock (PLLREF) and output clock (PLLOUT) for the block labeled PLL in Figure 15, as well as for the DSP core,
peripheral bus, and EMIF. The clock generator must not be configured to exceed any of these constraints
(certain combinations of external clock input, internal dividers, and PLL multiply ratios might not be supported).
See Table 35 for the PLL clocks input and output frequency ranges.
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