TMS320C6713B Floating-Point Digital Signal Processor (Rev. A)
TMS320C6713B Floating-Point Digital Signal Processor (Rev. A)
TMS320C6713B Floating-Point Digital Signal Processor (Rev. A)
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SPRS294A − OCTOBER 2005 − REVISED NOVEMBER 2005<br />
CPU CSR register description<br />
The CPU control status register (CSR) contains the CPU ID and CPU <strong>Rev</strong>ision ID (bits 16−31) as well as the<br />
status of the device power-down modes [PWRD field (bits 15−10)], program and data cache control modes, the<br />
endian bit (EN, bit 8) and the global interrupt enable (GIE, bit 0) and previous GIE (PGIE, bit 1). Figure 13 and<br />
Table 24 identify the bit fields in the CPU CSR register.<br />
For more detailed information on the bit fields in the CPU CSR register, see the TMS320C6000 DSP Peripherals<br />
Overview Reference Guide (literature number SPRU190) and the TMS320C6000 CPU and Instruction Set<br />
Reference Guide (literature number SPRU189).<br />
31 24 23 16<br />
CPU ID<br />
R-0x02<br />
REVISION ID<br />
R-0x03<br />
15 10 9 8 7 6 5 4 2 1 0<br />
PWRD SAT EN PCC DCC PGIE GIE<br />
R/W-0 R/C-0 R-1 R/W-0 R/W-0 R/W-0 R/W-0<br />
Legend: R = Readable by the MVC instruction, R/W = Readable/Writeable by the MVC instruction; W = Read/write; -n = value after reset, -x = undefined value after<br />
reset, C = Clearable by the MVC instruction<br />
Figure 13. CPU Control Status Register (CPU CSR)<br />
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