TMS320C6713B Floating-Point Digital Signal Processor (Rev. A)

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SPRS294A − OCTOBER 2005 − REVISED NOVEMBER 2005 DSP INTERRUPT NUMBER Table 26. DSP Interrupts INTERRUPT SELECTOR CONTROL REGISTER DEFAULT SELECTOR VALUE (BINARY) DEFAULT INTERRUPT EVENT INTERRUPT SELECTOR VALUE (BINARY) Table 27. Interrupt Selector INTERRUPT EVENT MODULE INT_00 − − RESET 00000 DSPINT HPI INT_01 − − NMI 00001 TINT0 Timer 0 INT_02 − − Reserved 00010 TINT1 Timer 1 INT_03 − − Reserved 00011 SDINT EMIF INT_04 MUXL[4:0] 00100 GPINT4† 00100 GPINT4† GPIO INT_05 MUXL[9:5] 00101 GPINT5† 00101 GPINT5† GPIO INT_06 MUXL[14:10] 00110 GPINT6† 00110 GPINT6† GPIO INT_07 MUXL[20:16] 00111 GPINT7† 00111 GPINT7† GPIO INT_08 MUXL[25:21] 01000 EDMAINT 01000 EDMAINT EDMA INT_09 MUXL[30:26] 01001 EMUDTDMA 01001 EMUDTDMA Emulation INT_10 MUXH[4:0] 00011 SDINT 01010 EMURTDXRX Emulation INT_11 MUXH[9:5] 01010 EMURTDXRX 01011 EMURTDXTX Emulation INT_12 MUXH[14:10] 01011 EMURTDXTX 01100 XINT0 McBSP0 INT_13 MUXH[20:16] 00000 DSPINT 01101 RINT0 McBSP0 INT_14 MUXH[25:21] 00001 TINT0 01110 XINT1 McBSP1 INT_15 MUXH[30:26] 00010 TINT1 01111 RINT1 McBSP1 10000 GPINT0 GPIO 10001 Reserved − 10010 Reserved − 10011 Reserved − 10100 Reserved − 10101 Reserved − 10110 I2CINT0 I2C0 10111 I2CINT1 I2C1 11000 Reserved − 11001 Reserved − 11010 Reserved − 11011 Reserved − 11100 AXINT0 McASP0 11101 ARINT0 McASP0 11110 AXINT1 McASP1 11111 ARINT1 McASP1 † Interrupt Events GPINT4, GPINT5, GPINT6, and GPINT7 are outputs from the GPIO module (GP). They originate from the device pins GP[4](EXT_INT4)/AMUTEIN1, GP[5](EXT_INT5)/AMUTEIN0, GP[6](EXT_INT6), and GP[7](EXT_INT7). These pins can be used as edge-sensitive EXT_INTx with polarity controlled by the External Interrupt Polarity Register (EXTPOL.[3:0]). The corresponding pins must first be enabled in the GPIO module by setting the corresponding enable bits in the GP Enable Register (GPEN.[7:4]), and configuring them as inputs in the GP Direction Register (GPDIR.[7:4]). These interrupts can be controlled through the GPIO module in addition to the simple EXTPOL.[3:0] bits. For more information on interrupt control via the GPIO module, see the TMS320C6000 DSP General-Purpose Input/Output (GPIO) Reference Guide (literature number SPRU584). 72 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
SPRS294A − OCTOBER 2005 − REVISED NOVEMBER 2005 external interrupt sources The device supports many external interrupt sources as indicated in Table 28. Control of the interrupt source is done by the associated module and is made available by enabling the corresponding binary interrupt selector value (see Table 27 Interrupt Selector shaded rows). Due to pin muxing and module usage, not all external interrupt sources are available at the same time. Table 28. External Interrupt Sources and Peripheral Module Control PIN NAME INTERRUPT EVENT MODULE GP[15] GPINT0 GPIO GP[14] GPINT0 GPIO GP[13] GPINT0 GPIO GP[12] GPINT0 GPIO GP[11] GPINT0 GPIO GP[10] GPINT0 GPIO GP[9] GPINT0 GPIO GP[8] GPINT0 GPIO GP[7] GPINT0 or GPINT7 GPIO GP[6] GPINT0 or GPINT6 GPIO GP[5] GPINT0 or GPINT5 GPIO GP[4] GPINT0 or GPINT4 GPIO GP[3] GPINT0 GPIO GP[2] GPINT0 GPIO GP[1] GPINT0 GPIO GP[0] GPINT0 GPIO POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 73
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SPRS294A − OCTOBER 2005 − REVIS
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REVISION HISTORY SPRS294A − OCTOB
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GDP and ZDP 272-Ball BGA package (b
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functional block and CPU (DSP core)
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Á Á Á Á Á Á ÁÁÁÁÁ ÁÁÁ
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Page 35 and 36: DEVICE CONFIGURATIONS (CONTINUED) p
Page 37 and 38: DEVICE CONFIGURATIONS (CONTINUED) S
Page 39 and 40: MULTIPLEXED PINS NAME PYP GDP/ ZDP
Page 41 and 42: configuration examples (continued)
Page 47 and 48: DEVICE CONFIGURATIONS (CONTINUED) S
Page 49 and 50: SIGNAL NAME PYP PIN NO. GDP/ ZDP TY
Page 51 and 52: SIGNAL NAME PYP PIN NO. GDP/ ZDP HD
Page 53 and 54: SIGNAL NAME PYP PIN NO. GDP/ ZDP ED
Page 55 and 56: SIGNAL NAME PYP PIN NO. GDP/ ZDP TY
Page 57 and 58: SIGNAL NAME PYP PIN NO. GDP/ ZDP SP
Page 59 and 60: SIGNAL NAME PYP PIN NO. GDP/ ZDP 11
Page 61 and 62: VSS SIGNAL NAME PYP PIN NO. GDP/ ZD
Page 63 and 64: VSS SIGNAL NAME PYP PIN NO. GDP/ ZD
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Page 75 and 76: EDMA module and EDMA selector (cont
Page 77 and 78: PLL and PLL controller SPRS294A −
Page 85 and 86: multichannel audio serial port (McA
Page 87 and 88: multichannel audio serial port (McA
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Page 101 and 102: PARAMETER MEASUREMENT INFORMATION S
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Page 105 and 106: INPUT AND OUTPUT CLOCKS SPRS294 −
Page 107 and 108: INPUT AND OUTPUT CLOCKS (CONTINUED)
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Page 111 and 112: SYNCHRONOUS-BURST MEMORY TIMING tim
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Page 115 and 116: SYNCHRONOUS DRAM TIMING (CONTINUED)
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Page 121 and 122: timing requirements for reset †
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EXTERNAL INTERRUPT TIMING SPRS294
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MULTICHANNEL AUDIO SERIAL PORT (McA
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INTER-INTEGRATED CIRCUITS (I2C) TIM
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HOST-PORT INTERFACE TIMING SPRS294
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HOST-PORT INTERFACE TIMING (CONTINU
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MULTICHANNEL BUFFERED SERIAL PORT T
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SPRS294 − OCTOBER 2005 switching
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GENERAL-PURPOSE INPUT/OUTPUT (GPIO)
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MECHANICAL DATA SPRS294 − OCTOBER
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SPRS294 − OCTOBER 2005 packaging
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MECHANICAL DATA MPBG274 - MAY 2002
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IMPORTANT NOTICE Texas Instruments
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TMS320C6713B Floating-Point Digital Signal Processor (Rev. A)

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