TMS320C6713B Floating-Point Digital Signal Processor (Rev. A)

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SPRS294A − OCTOBER 2005 − REVISED NOVEMBER 2005 EDMA module and EDMA selector The C67x EDMA supports up to 16 EDMA channels. Four of the sixteen channels (channels 8−11) are reserved for EDMA chaining, leaving 12 EDMA channels available to service peripheral devices. The EDMA selector registers that control the EDMA channels servicing peripheral devices are located at addresses 0x01A0FF00 (ESEL0), 0x01A0FF04 (ESEL1), and 0x01A0FF0C (ESEL3). These EDMA selector registers control the mapping of the EDMA events to the EDMA channels. Each EDMA event has an assigned EDMA selector code (see Table 30). By loading each EVTSELx register field with an EDMA selector code, users can map any desired EDMA event to any specified EDMA channel. Table 29 lists the default EDMA selector value for each EDMA channel. See Table 31 and Table 32 for the EDMA Event Selector registers and their associated bit descriptions. 74 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
EDMA module and EDMA selector (continued) EDMA CHANNEL Table 29. EDMA Channels EDMA SELECTOR CONTROL REGISTER DEFAULT SELECTOR VALUE (BINARY) DEFAULT EDMA EVENT SPRS294A − OCTOBER 2005 − REVISED NOVEMBER 2005 EDMA SELECTOR CODE (BINARY) Table 30. EDMA Selector EDMA EVENT MODULE 0 ESEL0[5:0] 000000 DSPINT 000000 DSPINT HPI 1 ESEL0[13:8] 000001 TINT0 000001 TINT0 TIMER0 2 ESEL0[21:16] 000010 TINT1 000010 TINT1 TIMER1 3 ESEL0[29:24] 000011 SDINT 000011 SDINT EMIF 4 ESEL1[5:0] 000100 GPINT4 000100 GPINT4 GPIO 5 ESEL1[13:8] 000101 GPINT5 000101 GPINT5 GPIO 6 ESEL1[21:16] 000110 GPINT6 000110 GPINT6 GPIO 7 ESEL1[29:24] 000111 GPINT7 000111 GPINT7 GPIO 8 − − TCC8 (Chaining) 001000 GPINT0 GPIO 9 − − TCC9 (Chaining) 001001 GPINT1 GPIO 10 − − TCC10 (Chaining) 001010 GPINT2 GPIO 11 − − TCC11 (Chaining) 001011 GPINT3 GPIO 12 ESEL3[5:0] 001100 XEVT0 001100 XEVT0 McBSP0 13 ESEL3[13:8] 001101 REVT0 001101 REVT0 McBSP0 14 ESEL3[21:16] 001110 XEVT1 001110 XEVT1 McBSP1 15 ESEL3[29:24] 001111 REVT1 001111 REVT1 McBSP1 010000−011111 Reserved 100000 AXEVTE0 McASP0 100001 AXEVTO0 McASP0 100010 AXEVT0 McASP0 100011 AREVTE0 McASP0 100100 AREVTO0 McASP0 100101 AREVT0 McASP0 100110 AXEVTE1 McASP1 100111 AXEVTO1 McASP1 101000 AXEVT1 McASP1 101001 AREVTE1 McASP1 101010 AREVTO1 McASP1 101011 AREVT1 McASP1 101100 I2CREVT0 I2C0 101101 I2CXEVT0 I2C0 101110 I2CREVT1 I2C1 101111 I2CXEVT1 I2C1 110000 GPINT8 GPIO 110001 GPINT9 GPIO 110010 GPINT10 GPIO 110011 GPINT11 GPIO 110100 GPINT12 GPIO 110101 GPINT13 GPIO 110110 GPINT14 GPIO 110111 GPINT15 GPIO 111000−111111 Reserved POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 75
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SPRS294A − OCTOBER 2005 − REVIS
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REVISION HISTORY SPRS294A − OCTOB
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GDP and ZDP 272-Ball BGA package (b
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functional block and CPU (DSP core)
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Á Á Á Á Á Á ÁÁÁÁÁ ÁÁÁ
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Page 23 and 24: SPRS294A − OCTOBER 2005 − REVIS
Page 35 and 36: DEVICE CONFIGURATIONS (CONTINUED) p
Page 37 and 38: DEVICE CONFIGURATIONS (CONTINUED) S
Page 39 and 40: MULTIPLEXED PINS NAME PYP GDP/ ZDP
Page 41 and 42: configuration examples (continued)
Page 47 and 48: DEVICE CONFIGURATIONS (CONTINUED) S
Page 49 and 50: SIGNAL NAME PYP PIN NO. GDP/ ZDP TY
Page 51 and 52: SIGNAL NAME PYP PIN NO. GDP/ ZDP HD
Page 53 and 54: SIGNAL NAME PYP PIN NO. GDP/ ZDP ED
Page 55 and 56: SIGNAL NAME PYP PIN NO. GDP/ ZDP TY
Page 57 and 58: SIGNAL NAME PYP PIN NO. GDP/ ZDP SP
Page 59 and 60: SIGNAL NAME PYP PIN NO. GDP/ ZDP 11
Page 61 and 62: VSS SIGNAL NAME PYP PIN NO. GDP/ ZD
Page 63 and 64: VSS SIGNAL NAME PYP PIN NO. GDP/ ZD
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Page 77 and 78: PLL and PLL controller SPRS294A −
Page 85 and 86: multichannel audio serial port (McA
Page 87 and 88: multichannel audio serial port (McA
Page 99 and 100: SPRS294 − OCTOBER 2005 absolute m
Page 101 and 102: PARAMETER MEASUREMENT INFORMATION S
Page 103 and 104: PARAMETER MEASUREMENT INFORMATION (
Page 105 and 106: INPUT AND OUTPUT CLOCKS SPRS294 −
Page 107 and 108: INPUT AND OUTPUT CLOCKS (CONTINUED)
Page 109 and 110: ASYNCHRONOUS MEMORY TIMING (CONTINU
Page 111 and 112: SYNCHRONOUS-BURST MEMORY TIMING tim
Page 113 and 114: SYNCHRONOUS DRAM TIMING timing requ
Page 115 and 116: SYNCHRONOUS DRAM TIMING (CONTINUED)
Page 117 and 118: SYNCHRONOUS DRAM TIMING (CONTINUED)
Page 119 and 120: HOLD/HOLDA TIMING SPRS294 − OCTOB
Page 121 and 122: timing requirements for reset †
Page 123 and 124: EXTERNAL INTERRUPT TIMING SPRS294
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MULTICHANNEL AUDIO SERIAL PORT (McA
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INTER-INTEGRATED CIRCUITS (I2C) TIM
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HOST-PORT INTERFACE TIMING SPRS294
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HOST-PORT INTERFACE TIMING (CONTINU
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MULTICHANNEL BUFFERED SERIAL PORT T
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SPRS294 − OCTOBER 2005 switching
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GENERAL-PURPOSE INPUT/OUTPUT (GPIO)
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MECHANICAL DATA SPRS294 − OCTOBER
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SPRS294 − OCTOBER 2005 packaging
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MECHANICAL DATA MPBG274 - MAY 2002
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IMPORTANT NOTICE Texas Instruments
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TMS320C6713B Floating-Point Digital Signal Processor (Rev. A)

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