TMS320C6713B Floating-Point Digital Signal Processor (Rev. A)
TMS320C6713B Floating-Point Digital Signal Processor (Rev. A)
TMS320C6713B Floating-Point Digital Signal Processor (Rev. A)
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MULTICHANNEL AUDIO SERIAL PORT (McASP) TIMING (CONTINUED)<br />
SPRS294 − OCTOBER 2005<br />
AHCLKR/X (Falling Edge Polarity)<br />
1<br />
2<br />
2<br />
AHCLKR/X (Rising Edge Polarity)<br />
ACLKR/X (CLKRP = CLKXP = 0)†<br />
3<br />
4<br />
4<br />
ACLKR/X (CLKRP = CLKXP = 1)‡<br />
AFSR/X (Bit Width, 0 Bit Delay)<br />
6<br />
5<br />
AFSR/X (Bit Width, 1 Bit Delay)<br />
AFSR/X (Bit Width, 2 Bit Delay)<br />
AFSR/X (Slot Width, 0 Bit Delay)<br />
AFSR/X (Slot Width, 1 Bit Delay)<br />
AFSR/X (Slot Width, 2 Bit Delay)<br />
AXR[n] (Data In/Receive)<br />
8<br />
7<br />
A0 A1 A30 A31 B0 B1 B30 B31 C0 C1 C2 C3 C31<br />
† For CLKRP = CLKXP = 0, the McASP transmitter is configured for rising edge (to shift data out) and the McASP receiver is configured for falling<br />
edge (to shift data in).<br />
‡ For CLKRP = CLKXP = 1, the McASP transmitter is configured for falling edge (to shift data out) and the McASP receiver is configured for rising<br />
edge (to shift data in).<br />
Figure 51. McASP Input Timings<br />
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443<br />
125
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