TMS320C6713B Floating-Point Digital Signal Processor (Rev. A)
TMS320C6713B Floating-Point Digital Signal Processor (Rev. A)
TMS320C6713B Floating-Point Digital Signal Processor (Rev. A)
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SPRS294 − OCTOBER 2005<br />
SYNCHRONOUS DRAM TIMING (CONTINUED)<br />
READ<br />
ECLKOUT<br />
CEx<br />
1<br />
1<br />
BE[3:0]<br />
2<br />
BE1 BE2 BE3 BE4<br />
3<br />
EA[21:13]<br />
4<br />
Bank<br />
5<br />
EA[11:2]<br />
4<br />
Column<br />
5<br />
EA12<br />
ED[31:0]<br />
4<br />
5<br />
6<br />
7<br />
D1 D2 D3 D4<br />
AOE/SDRAS/SSOE†<br />
ARE/SDCAS/SSADS†<br />
8<br />
8<br />
AWE/SDWE/SSWE†<br />
† ARE/SDCAS/SSADS, AWE/SDWE/SSWE, and AOE/SDRAS/SSOE operate as SDCAS, SDWE, and SDRAS, respectively, during SDRAM<br />
accesses.<br />
Figure 40. SDRAM Read Command (CAS Latency 3)<br />
114 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443