TMS320C6713B Floating-Point Digital Signal Processor (Rev. A)
TMS320C6713B Floating-Point Digital Signal Processor (Rev. A)
TMS320C6713B Floating-Point Digital Signal Processor (Rev. A)
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SPRS294 − OCTOBER 2005<br />
ASYNCHRONOUS MEMORY TIMING<br />
timing requirements for asynchronous memory cycles †‡§ (see Figure 36−Figure 37)<br />
NO.<br />
PYP-200,-225<br />
GDP/ZDP -225, -300<br />
PYPA −167, -200 UNIT<br />
GDPA/ZDPA −200<br />
MIN MAX<br />
3 tsu(EDV-AREH) Setup time, EDx valid before ARE high 6.5 ns<br />
4 th(AREH-EDV) Hold time, EDx valid after ARE high 1 ns<br />
6 tsu(ARDY-EKOH) Setup time, ARDY valid before ECLKOUT high 3 ns<br />
7 th(EKOH-ARDY) Hold time, ARDY valid after ECLKOUT high 2.3 ns<br />
† To ensure data setup time, simply program the strobe width wide enough. ARDY is internally synchronized. The ARDY signal is recognized in<br />
the cycle for which the setup and hold time is met. To use ARDY as an asynchronous input, the pulse width of the ARDY signal should be wide<br />
enough (e.g., pulse width = 2E) to ensure setup and hold time is met.<br />
‡ RS = Read setup, RST = Read strobe, RH = Read hold, WS = Write setup, WST = Write strobe, WH = Write hold. These parameters are<br />
programmed via the EMIF CE space control registers.<br />
§ E = ECLKOUT period in ns<br />
switching characteristics over recommended operating conditions for asynchronous memory<br />
cycles ‡§ (see Figure 36−Figure 37)<br />
NO.<br />
PARAMETER<br />
PYP-200,-225<br />
GDP/ZDP -225, -300<br />
PYPA -167, -200 UNIT<br />
GDPA/ZDPA −200<br />
MIN MAX<br />
1 tosu(SELV-AREL) Output setup time, select signals valid to ARE low RS*E − 1.7 ns<br />
2 toh(AREH-SELIV) Output hold time, ARE high to select signals invalid RH*E − 1.7 ns<br />
5 td(EKOH-AREV) Delay time, ECLKOUT high to ARE valid 1.5 7 ns<br />
8 tosu(SELV-AWEL) Output setup time, select signals valid to AWE low WS*E − 1.7 ns<br />
9 toh(AWEH-SELIV) Output hold time, AWE high to select signals and EDx invalid WH*E − 1.7 ns<br />
10 td(EKOH-AWEV) Delay time, ECLKOUT high to AWE valid 1.5 7 ns<br />
11 tosu(EDV-AWEL) Output setup time, ED valid to AWE low<br />
(WS−1)*E −<br />
1.7<br />
‡ RS = Read setup, RST = Read strobe, RH = Read hold, WS = Write setup, WST = Write strobe, WH = Write hold. These parameters are<br />
programmed via the EMIF CE space control registers.<br />
§ E = ECLKOUT period in ns<br />
Select signals include: CEx, BE[3:0], EA[21:2], and AOE.<br />
ns<br />
108 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
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