TMS320C6713B Floating-Point Digital Signal Processor (Rev. A)

SPRS294A − OCTOBER 2005 − REVISED NOVEMBER 2005
bootmode
reset
The device resets using the active-low signal RESET and the internal reset signal. While RESET is low, the
internal reset is also asserted and the device is held in reset and is initialized to the prescribed reset state. Refer
to reset timing for reset timing characteristics and states of device pins during reset. The release of the internal
reset signal (see the Reset Phase 3 discussion in the Reset Timing section of this data sheet) starts the
processor running with the prescribed device configuration and boot mode.
The C6713B has three types of boot modes:
Host boot
If host boot is selected, upon release of internal reset, the CPU is internally “stalled” while the remainder of
the device is released. During this period, an external host can initialize the CPU’s memory space as
necessary through the host interface, including internal configuration registers, such as those that control
the EMIF or other peripherals. Once the host is finished with all necessary initialization, it must set the
DSPINT bit in the HPIC register to complete the boot process. This transition causes the boot configuration
logic to bring the CPU out of the “stalled” state. The CPU then begins execution from address 0. The DSPINT
condition is not latched by the CPU, because it occurs while the CPU is still internally “stalled”. Also, DSPINT
brings the CPU out of the “stalled” state only if the host boot process is selected. All memory may be written
to and read by the host. This allows for the host to verify what it sends to the DSP if required. After the CPU is
out of the “stalled” state , the CPU needs to clear the DSPINT, otherwise, no more DSPINTs can be received.
Emulation boot
Emulation boot mode is a variation of host boot. In this mode, it is not necessary for a host to load code or to
set DSPINT to release the CPU from the “stalled” state. Instead, the emulator will set DSPINT if it has not
been previously set so that the CPU can begin executing code from address 0. Prior to beginning execution,
the emulator sets a breakpoint at address 0. This prevents the execution of invalid code by halting the CPU
prior to executing the first instruction. Emulation boot is a good tool in the debug phase of development.
EMIF boot (using default ROM timings)
Upon the release of internal reset, the 1K-Byte ROM code located in the beginning of CE1 is copied to
address 0 by the EDMA using the default ROM timings, while the CPU is internally “stalled”. The data should
be stored in the endian format that the system is using. The boot process also lets you choose the width of
the ROM. In this case, the EMIF automatically assembles consecutive 8-bit bytes or 16-bit half-words to
form the 32-bit instruction words to be copied. The transfer is automatically done by the EDMA as a
single-frame block transfer from the ROM to address 0. After completion of the block transfer, the CPU is
released from the “stalled” state and start running from address 0.
A hardware reset (RESET) is required to place the DSP into a known good state out of power−up. The RESET
signal can be asserted (pulled low) prior to ramping the core and I/O voltages or after the core and I/O voltages
have reached their proper operating conditions. As a best practice, reset should be held low during power−up.
Prior to deasserting RESET (low−to−high transition), the core and I/O voltages should be at their proper
operating conditions and CLKIN should also be running at the correct frequency.
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