TMS320C6713B Floating-Point Digital Signal Processor (Rev. A)

SYNCHRONOUS-BURST MEMORY TIMING
timing requirements for synchronous-burst SRAM cycles † (see Figure 38)
SPRS294 − OCTOBER 2005
NO.
PYP-200,-225
GDP/ZDP -225, -300
PYPA -167, -200 UNIT
GDPA/ZDPA −200
MIN MAX
6 tsu(EDV-EKOH) Setup time, read EDx valid before ECLKOUT high 1.5 ns
7 th(EKOH-EDV) Hold time, read EDx valid after ECLKOUT high 2.5 ns
† The C6713B SBSRAM interface takes advantage of the internal burst counter in the SBSRAM. Accesses default to incrementing 4-word bursts,
but random bursts and decrementing bursts are done by interrupting bursts in progress. All burst types can sustain continuous data flow.
switching characteristics over recommended operating conditions for synchronous-burst SRAM
cycles †‡ (see Figure 38 and Figure 39)
NO.
PARAMETER
PYP-200,-225
GDP/ZDP -225, -300
PYPA
-167, -200
GDPA/ZDPA −200
UNIT
MIN MAX
1 td(EKOH-CEV) Delay time, ECLKOUT high to CEx valid 1.2 7 ns
2 td(EKOH-BEV) Delay time, ECLKOUT high to BEx valid 7 ns
3 td(EKOH-BEIV) Delay time, ECLKOUT high to BEx invalid 1.2 ns
4 td(EKOH-EAV) Delay time, ECLKOUT high to EAx valid 7 ns
5 td(EKOH-EAIV) Delay time, ECLKOUT high to EAx invalid 1.2 ns
8 td(EKOH-ADSV) Delay time, ECLKOUT high to ARE/SDCAS/SSADS valid 1.2 7 ns
9 td(EKOH-OEV) Delay time, ECLKOUT high to, AOE/SDRAS/SSOE valid 1.2 7 ns
10 td(EKOH-EDV) Delay time, ECLKOUT high to EDx valid 7 ns
11 td(EKOH-EDIV) Delay time, ECLKOUT high to EDx invalid 1.2 ns
12 td(EKOH-WEV) Delay time, ECLKOUT high to AWE/SDWE/SSWE valid 1.2 7 ns
† The C6713B SBSRAM interface takes advantage of the internal burst counter in the SBSRAM. Accesses default to incrementing 4-word bursts,
but random bursts and decrementing bursts are done by interrupting bursts in progress. All burst types can sustain continuous data flow.
‡ ARE/SDCAS/SSADS, AOE/SDRAS/SSOE, and AWE/SDWE/SSWE operate as SSADS, SSOE, and SSWE, respectively, during SBSRAM
accesses.
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
111