TMS320C6713B Floating-Point Digital Signal Processor (Rev. A)

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SPRS294 − OCTOBER 2005 PARAMETER MEASUREMENT INFORMATION (CONTINUED) Table 46. Board-Level Timings Example (see Figure 30) NO. DESCRIPTION 1 Clock route delay 2 Minimum DSP hold time 3 Minimum DSP setup time 4 External device hold time requirement 5 External device setup time requirement 6 Control signal route delay 7 External device hold time 8 External device access time 9 DSP hold time requirement 10 DSP setup time requirement 11 Data route delay ECLKOUT (Output from DSP) ECLKOUT (Input to External Device) Control Signals† (Output from DSP) Control Signals (Input to External Device) Data Signals‡ (Output from External Device) Data Signals‡ (Input to DSP) 3 6 8 5 11 1 2 4 10 9 7 † Control signals include data for Writes. ‡ Data signals are generated during Reads from an external device. Figure 30. Board-Level Input/Output Timings 104 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
INPUT AND OUTPUT CLOCKS SPRS294 − OCTOBER 2005 timing requirements for CLKIN for PYP-200 and GDP/ZDP-225 †‡§ (see Figure 31) NO. PLL MODE (PLLEN = 1) PYP−200 BYPASS MODE (PLLEN = 0) PLL MODE (PLLEN = 1) GDP/ZDP−225 BYPASS MODE (PLLEN = 0) MIN MAX MIN MAX MIN MAX MIN MAX 1 tc(CLKIN) Cycle time, CLKIN 5 83.3 6.7 4.4 83.3 6.7 ns 2 tw(CLKINH) Pulse duration, CLKIN high 0.4C 0.4C 0.4C 0.4C ns 3 tw(CLKINL) Pulse duration, CLKIN low 0.4C 0.4C 0.4C 0.4C ns 4 tt(CLKIN) Transition time, CLKIN 5 5 5 5 ns † The reference points for the rise and fall transitions are measured at VIL MAX and VIH MIN. ‡ C = CLKIN cycle time in nanoseconds (ns). For example, when CLKIN frequency is 40 MHz, use C = 25 ns. § See the PLL and PLL controller section of this data sheet. UNIT timing requirements for CLKIN for PYP-225 and GDP/ZDP-300 †‡§ (see Figure 31) NO. PLL MODE (PLLEN = 1) PYP−225 BYPASS MODE (PLLEN = 0) PLL MODE (PLLEN = 1) GDP/ZDP−300 BYPASS MODE (PLLEN = 0) MIN MAX MIN MAX MIN MAX MIN MAX 1 tc(CLKIN) Cycle time, CLKIN 4.4 83.3 6.7 4 83.3 6.7 ns 2 tw(CLKINH) Pulse duration, CLKIN high 0.4C 0.4C 0.4C 0.4C ns 3 tw(CLKINL) Pulse duration, CLKIN low 0.4C 0.4C 0.4C 0.4C ns 4 tt(CLKIN) Transition time, CLKIN 5 5 5 5 ns † The reference points for the rise and fall transitions are measured at VIL MAX and VIH MIN. ‡ C = CLKIN cycle time in nanoseconds (ns). For example, when CLKIN frequency is 40 MHz, use C = 25 ns. § See the PLL and PLL controller section of this data sheet. UNIT timing requirements for CLKIN for PYPA-167, GDPA/ZDPA-200 and PYPA-200 †‡§ (see Figure 31) NO. PLL MODE (PLLEN = 1) PYPA−167 BYPASS MODE (PLLEN = 0) GDPA/ZDPA−200 AND PYPA−200 PLL MODE (PLLEN = 1) BYPASS MODE (PLLEN = 0) MIN MAX MIN MAX MIN MAX MIN MAX 1 tc(CLKIN) Cycle time, CLKIN 6 83.3 6.7 5 83.3 6.7 ns 2 tw(CLKINH) Pulse duration, CLKIN high 0.4C 0.4C 0.4C 0.4C ns 3 tw(CLKINL) Pulse duration, CLKIN low 0.4C 0.4C 0.4C 0.4C ns 4 tt(CLKIN) Transition time, CLKIN 5 5 5 5 ns † The reference points for the rise and fall transitions are measured at VIL MAX and VIH MIN. ‡ C = CLKIN cycle time in nanoseconds (ns). For example, when CLKIN frequency is 40 MHz, use C = 25 ns. § See the PLL and PLL controller section of this data sheet. UNIT 2 1 4 CLKIN 3 4 Figure 31. CLKIN Timings POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 105
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SPRS294A − OCTOBER 2005 − REVIS
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REVISION HISTORY SPRS294A − OCTOB
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GDP and ZDP 272-Ball BGA package (b
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functional block and CPU (DSP core)
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DEVICE CONFIGURATIONS (CONTINUED) p
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DEVICE CONFIGURATIONS (CONTINUED) S
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MULTIPLEXED PINS NAME PYP GDP/ ZDP
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configuration examples (continued)
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DEVICE CONFIGURATIONS (CONTINUED) S
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SIGNAL NAME PYP PIN NO. GDP/ ZDP TY
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SIGNAL NAME PYP PIN NO. GDP/ ZDP HD
Page 53 and 54: SIGNAL NAME PYP PIN NO. GDP/ ZDP ED
Page 55 and 56: SIGNAL NAME PYP PIN NO. GDP/ ZDP TY
Page 57 and 58: SIGNAL NAME PYP PIN NO. GDP/ ZDP SP
Page 59 and 60: SIGNAL NAME PYP PIN NO. GDP/ ZDP 11
Page 61 and 62: VSS SIGNAL NAME PYP PIN NO. GDP/ ZD
Page 63 and 64: VSS SIGNAL NAME PYP PIN NO. GDP/ ZD
Page 65 and 66: SPRS294A − OCTOBER 2005 − REVIS
Page 75 and 76: EDMA module and EDMA selector (cont
Page 77 and 78: PLL and PLL controller SPRS294A −
Page 85 and 86: multichannel audio serial port (McA
Page 87 and 88: multichannel audio serial port (McA
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Page 101 and 102: PARAMETER MEASUREMENT INFORMATION S
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Page 107 and 108: INPUT AND OUTPUT CLOCKS (CONTINUED)
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Page 113 and 114: SYNCHRONOUS DRAM TIMING timing requ
Page 115 and 116: SYNCHRONOUS DRAM TIMING (CONTINUED)
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Page 119 and 120: HOLD/HOLDA TIMING SPRS294 − OCTOB
Page 121 and 122: timing requirements for reset †
Page 123 and 124: EXTERNAL INTERRUPT TIMING SPRS294
Page 125 and 126: MULTICHANNEL AUDIO SERIAL PORT (McA
Page 127 and 128: INTER-INTEGRATED CIRCUITS (I2C) TIM
Page 129 and 130: HOST-PORT INTERFACE TIMING SPRS294
Page 131 and 132: HOST-PORT INTERFACE TIMING (CONTINU
Page 133 and 134: MULTICHANNEL BUFFERED SERIAL PORT T
Page 139 and 140: SPRS294 − OCTOBER 2005 switching
Page 143 and 144: GENERAL-PURPOSE INPUT/OUTPUT (GPIO)
Page 145 and 146: MECHANICAL DATA SPRS294 − OCTOBER
Page 147 and 148: SPRS294 − OCTOBER 2005 packaging
Page 149 and 150: MECHANICAL DATA MPBG274 - MAY 2002
Page 152: IMPORTANT NOTICE Texas Instruments
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TMS320C6713B Floating-Point Digital Signal Processor (Rev. A)

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