TMS320C6713B Floating-Point Digital Signal Processor (Rev. A)
TMS320C6713B Floating-Point Digital Signal Processor (Rev. A)
TMS320C6713B Floating-Point Digital Signal Processor (Rev. A)
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SPRS294A − OCTOBER 2005 − REVISED NOVEMBER 2005<br />
multichannel audio serial port (McASP) peripherals<br />
The device includes two multi-channel audio serial port (McASP) interface peripherals (McASP1 and McASP0).<br />
The McASP is a serial port optimized for the needs of multi-channel audio applications. With two McASP<br />
peripherals, the device is capable of supporting two completely independent audio zones simultaneously.<br />
Each McASP consists of a transmit and receive section. These sections can operate completely independently<br />
with different data formats, separate master clocks, bit clocks, and frame syncs or alternatively, the transmit and<br />
receive sections may be synchronized. Each McASP module also includes a pool of 16 shift registers that may<br />
be configured to operate as either transmit data, receive data, or general-purpose I/O (GPIO).<br />
The transmit section of the McASP can transmit data in either a time-division-multiplexed (TDM) synchronous<br />
serial format or in a digital audio interface (DIT) format where the bit stream is encoded for S/PDIF, AES-3,<br />
IEC-60958, CP-430 transmission. The receive section of the McASP supports the TDM synchronous serial<br />
format.<br />
Each McASP can support one transmit data format (either a TDM format or DIT format) and one receive format<br />
at a time. All transmit shift registers use the same format and all receive shift registers use the same format.<br />
However, the transmit and receive formats need not be the same.<br />
Both the transmit and receive sections of the McASP also support burst mode which is useful for non-audio data<br />
(for example, passing control information between two DSPs).<br />
The McASP peripherals have additional capability for flexible clock generation, and error detection/handling,<br />
as well as error management.<br />
McASP block diagram<br />
Figure 16 illustrates the major blocks along with external signals of the McASP1 and McASP0 peripherals; and<br />
shows the 8 serial data [AXR] pins for each McASP. Each McASP also includes full general-purpose I/O (GPIO)<br />
control, so any pins not needed for serial transfers can be used for general-purpose I/O.<br />
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