TMS320C6713B Floating-Point Digital Signal Processor (Rev. A)

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SPRS294A − OCTOBER 2005 − REVISED NOVEMBER 2005 peripheral pin selection at device reset DEVICE CONFIGURATIONS (CONTINUED) Some peripherals share the same pins (internally muxed) and are mutually exclusive (i.e., HPI, general-purpose input/output pins GP[15:8, 3, 1, 0] and McASP1). HPI, McASP1, and GPIO peripherals The HPI_EN (HD14 pin) is latched at reset. This pin selects whether the HPI peripheral pins or McASP1 peripheral pins and GP[15:8, 3, 1, 0] pins are functionally enabled (see Table 19). Table 19. HPI_EN (HD14 Pin) Peripheral Selection (HPI or McASP1, and Select GPIO Pins) † PERIPHERAL PIN SELECTION HPI_EN (HD14 Pin) [173, C14] PERIPHERAL PINS SELECTED McASP1 and HPI GP[15:8,3,1,0] 0 √ 1 √ † The HPI_EN (HD[14]) pin cannot be controlled via software. DESCRIPTION HPI_EN = 0 HPI pins are disabled; McASP1 peripheral pins and GP[15:8, 3, 1,0] pins are enabled. All multiplexed HPI/McASP1 and HPI/GPIO pins function as McASP1 and GPIO pins, respectively. To use the GPIO pins, the appropriate bits in the GPEN and GPDIR registers need to be configured. HPI_EN = 1 HPI pins are enabled; McASP1 peripheral pins and GP[15:8, 3, 1,0] pins are disabled [default]. All multiplexed HPI/McASP1 and HPI/GPIO pins function as HPI pins. 34 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
DEVICE CONFIGURATIONS (CONTINUED) peripheral selection/device configurations via the DEVCFG control register SPRS294A − OCTOBER 2005 − REVISED NOVEMBER 2005 The device configuration register (DEVCFG) allows the user to control the pin availability of the McBSP0, McBSP1, McASP0, I2C1, and Timer peripherals. The DEVCFG register also offers the user control of the EMIF input clock source and the timer output pins. For more detailed information on the DEVCFG register control bits, see Table 20 and Table 21. Table 20. Device Configuration Register (DEVCFG) [Address location: 0x019C0200 − 0x019C02FF] 31 16 Reserved† RW-0 15 5 4 3 2 1 0 Reserved† EKSRC TOUT1SEL TOUT0SEL MCBSP0DIS MCBSP1DIS Legend: R/W = Read/Write; -n = value after reset † Do not write non-zero values to these bit locations. RW-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 Table 21. Device Configuration (DEVCFG) Register Selection Bit Descriptions BIT # NAME DESCRIPTION 31:5 Reserved Reserved. Do not write non-zero values to these bit locations. 4 EKSRC 3 TOUT1SEL 2 TOUT0SEL 1 MCBSP0DIS 0 MCBSP1DIS EMIF input clock source bit. Determines which clock signal is used as the EMIF input clock. 0 = SYSCLK3 (from the clock generator) is the EMIF input clock source (default) 1 = ECLKIN external pin is the EMIF input clock source Timer 1 output (TOUT1) pin function select bit. Selects the pin function of the TOUT1/AXR0[4] external pin independent of the rest of the peripheral selection bits in the DEVCFG register. 0 = The pin functions as a Timer 1 output (TOUT1) pin (default) 1 = The pin functions as the McASP0 transmit/receive data pin 4 (AXR0[4]). The Timer 1 module is still active. Timer 0 output (TOUT0) pin function select bit. Selects the pin function of the TOUT0/AXR0[2] external pin independent of the rest of the peripheral selection bits in the DEVCFG register. 0 = The pin functions as a Timer 0 output (TOUT0) pin (default) 1 = The pin functions as the McASP0 transmit/receive data pin 2 (AXR0[2]). The Timer 0 module is still active. Multichannel Buffered Serial Port 0 (McBSP0) disable bit. Selects whether McBSP0 or the McASP0 multiplexed peripheral pins are enabled or disabled. 0 = McBSP0 peripheral pins are enabled, McASP0 peripheral pins (AHCLKR0, ACLKR0, ACLKX0, AXR0[0], AXR0[1], AFSR0, and AFSX0) are disabled (default). [If the McASP0 data pins are available, the McASP0 peripheral is functional for DIT mode only.] 1 = McBSP0 peripheral pins are disabled, McASP0 peripheral pins (AHCLKR0, ACLKR0, ACLKX0, AXR0[0], AXR0[1], AFSR0, and AFSX0) are enabled. Multichannel Buffered Serial Port 1 (McBSP1) disable bit. Selects whether McBSP1 or I2C1 and McASP0 multiplexed peripheral pins are enabled or disabled. 0 = McBSP1 peripheral pins are enabled, I2C1 peripheral pins (SCL1 and SDA1) and McASP0 peripheral pins (AXR0[7:5] and AMUTE0) are disabled (default) 1 = McBSP1 peripheral pins are disabled, I2C1 peripheral pins (SCL1 and SDA1) and McASP0 peripheral pins (AXR0[7:5] and AMUTE0) are enabled. POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 35
Page 1 and 2: SPRS294A − OCTOBER 2005 − REVIS
Page 3 and 4: REVISION HISTORY SPRS294A − OCTOB
Page 5 and 6: GDP and ZDP 272-Ball BGA package (b
Page 13 and 14: functional block and CPU (DSP core)
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Page 37 and 38: DEVICE CONFIGURATIONS (CONTINUED) S
Page 39 and 40: MULTIPLEXED PINS NAME PYP GDP/ ZDP
Page 41 and 42: configuration examples (continued)
Page 47 and 48: DEVICE CONFIGURATIONS (CONTINUED) S
Page 49 and 50: SIGNAL NAME PYP PIN NO. GDP/ ZDP TY
Page 51 and 52: SIGNAL NAME PYP PIN NO. GDP/ ZDP HD
Page 53 and 54: SIGNAL NAME PYP PIN NO. GDP/ ZDP ED
Page 55 and 56: SIGNAL NAME PYP PIN NO. GDP/ ZDP TY
Page 57 and 58: SIGNAL NAME PYP PIN NO. GDP/ ZDP SP
Page 59 and 60: SIGNAL NAME PYP PIN NO. GDP/ ZDP 11
Page 61 and 62: VSS SIGNAL NAME PYP PIN NO. GDP/ ZD
Page 63 and 64: VSS SIGNAL NAME PYP PIN NO. GDP/ ZD
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multichannel audio serial port (McA
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multichannel audio serial port (McA
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SPRS294A − OCTOBER 2005 − REVIS
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SPRS294 − OCTOBER 2005 absolute m
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PARAMETER MEASUREMENT INFORMATION S
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PARAMETER MEASUREMENT INFORMATION (
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INPUT AND OUTPUT CLOCKS SPRS294 −
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INPUT AND OUTPUT CLOCKS (CONTINUED)
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ASYNCHRONOUS MEMORY TIMING (CONTINU
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SYNCHRONOUS-BURST MEMORY TIMING tim
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SYNCHRONOUS DRAM TIMING timing requ
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SYNCHRONOUS DRAM TIMING (CONTINUED)
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SYNCHRONOUS DRAM TIMING (CONTINUED)
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HOLD/HOLDA TIMING SPRS294 − OCTOB
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timing requirements for reset †
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EXTERNAL INTERRUPT TIMING SPRS294
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MULTICHANNEL AUDIO SERIAL PORT (McA
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INTER-INTEGRATED CIRCUITS (I2C) TIM
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HOST-PORT INTERFACE TIMING SPRS294
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HOST-PORT INTERFACE TIMING (CONTINU
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MULTICHANNEL BUFFERED SERIAL PORT T
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SPRS294 − OCTOBER 2005 switching
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GENERAL-PURPOSE INPUT/OUTPUT (GPIO)
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MECHANICAL DATA SPRS294 − OCTOBER
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SPRS294 − OCTOBER 2005 packaging
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MECHANICAL DATA MPBG274 - MAY 2002
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IMPORTANT NOTICE Texas Instruments
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TMS320C6713B Floating-Point Digital Signal Processor (Rev. A)

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