TMS320C6713B Floating-Point Digital Signal Processor (Rev. A)

SPRS294 − OCTOBER 2005
INPUT AND OUTPUT CLOCKS (CONTINUED)
switching characteristics over recommended operating conditions for CLKOUT2 †‡
(see Figure 32)
NO.
PARAMETER
PYP −200, −225
GDP/ZDP −225, -300
PYPA −167, -200
GDPA/ZDPA −200
UNIT
MIN MAX
1 tc(CKO2) Cycle time, CLKOUT2 C2 − 0.8 C2 + 0.8 ns
2 tw(CKO2H) Pulse duration, CLKOUT2 high (C2/2) − 0.8 (C2/2) + 0.8 ns
3 tw(CKO2L) Pulse duration, CLKOUT2 low (C2/2) − 0.8 (C2/2) + 0.8 ns
4 tt(CKO2) Transition time, CLKOUT2 2 ns
† The reference points for the rise and fall transitions are measured at VOL MAX and VOH MIN.
‡ C2 = CLKOUT2 period in ns. CLKOUT2 period is determined by the PLL controller output SYSCLK2 period, which must be set to CPU period
divide-by-2.
1
4
2
CLKOUT2
Figure 32. CLKOUT2 Timings
switching characteristics over recommended operating conditions for CLKOUT3 †§
(see Figure 33)
NO.
PARAMETER
PYP −200, −225
GDP/ZDP −225, -300
PYPA −167, -200
GDPA/ZDPA −200
UNIT
MIN MAX
1 tc(CKO3) Cycle time, CLKOUT3 C3 − 0.9 C3 + 0.9 ns
2 tw(CKO3H) Pulse duration, CLKOUT3 high (C3/2) − 0.9 (C3/2) + 0.9 ns
3 tw(CKO3L) Pulse duration, CLKOUT3 low (C3/2) − 0.9 (C3/2) + 0.9 ns
4 tt(CKO3) Transition time, CLKOUT3 3 ns
5 td(CLKINH-CKO3V) Delay time, CLKIN high to CLKOUT3 valid 1.5 7.5 ns
† The reference points for the rise and fall transitions are measured at VOL MAX and VOH MIN.
§ C3 = CLKOUT3 period in ns. CLKOUT3 period is a divide-down of the CPU clock, configurable via the OSCDIV1 register. For more details, see
PLL and PLL controller.
CLKIN
3
4
CLKOUT3
3
1
4
5
5
2
4
NOTE A: For this example, the CLKOUT3 frequency is CLKIN divide-by-2.
Figure 33. CLKOUT3 Timings
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