TMS320C6713B Floating-Point Digital Signal Processor (Rev. A)

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SPRS294 − OCTOBER 2005 electrical characteristics over recommended ranges of supply voltage and operating case temperature † (unless otherwise noted) VOH VOL II IOZ IDD2V IDD3V PARAMETER TEST CONDITIONS MIN TYP MAX UNIT High-level output All signals except SCL1, SDA1, voltage SCL0, and SDA0 IOH =MAX 2.4 V Low-level output voltage Input current Off-state output current Core supply current‡ I/O supply current‡ All signals except SCL1, SDA1, SCL0, and SDA0 IOL = MAX 0.4 V SCL1, SDA1, SCL0, and SDA0 IOL = MAX 0.4 V All signals except SCL1, SDA1, SCL0, and SDA0 SCL1, SDA1, SCL0, and SDA0 All signals except SCL1, SDA1, SCL0, and SDA0 SCL1, SDA1, SCL0, and SDA0 VI = VSS to DVDD VO = DVDD or 0 V GDP/ZDP, CVDD = 1.4 V, CPU clock = 300 MHz GDP/ZDP/PYP, CVDD = 1.26 V, CPU clock = 225 MHz GDPA/ZDPA, CVDD =1.26V CPU clock = 200 MHz GDPA/ZDPA/PYP/ PYPA CVDD =1.2 V CPU clock = 200 MHz PYPA, CVDD =1.2 V CPU clock = 167 MHz DVDD = 3.3 V, EMIF speed = 100 MHz ±170 uA ±10 uA ±170 uA ±10 uA 945 mA 625 mA 560 mA 565 mA 480 mA 75 mA Ci Input capacitance 7 pF Co Output capacitance 7 pF † For test conditions shown as MIN, MAX, or NOM, use the appropriate value specified in the recommended operating conditions table. ‡ Measured with average activity (50% high/50% low power) at 25°C case temperature and 100-MHz EMIF. This model represents a device performing high-DSP-activity operations 50% of the time, and the remainder performing low-DSP-activity operations. The high/low-DSP-activity models are defined as follows: High-DSP-Activity Model: CPU: 8 instructions/cycle with 2 LDDW instructions [L1 Data Memory: 128 bits/cycle via LDDW instructions; L1 Program Memory: 256 bits/cycle; L2/EMIF EDMA: 50% writes, 50% reads to/from SDRAM (50% bit-switching)] McBSP: 2 channels at E1 rate Timers: 2 timers at maximum rate Low-DSP-Activity Model: CPU: 2 instructions/cycle with 1 LDH instruction [L1 Data Memory: 16 bits/cycle; L1 Program Memory: 256 bits per 4 cycles; L2/EMIF EDMA: None] McBSP: 2 channels at E1 rate Timers: 2 timers at maximum rate The actual current draw is highly application-dependent. For more details on core and I/O activity, refer to the TMS320C6711D, C6712D, C6713B Power Consumption Summary application report (literature number SPRA889A2 or later). 100 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
PARAMETER MEASUREMENT INFORMATION SPRS294 − OCTOBER 2005 Tester Pin Electronics Data Sheet Timing Reference <strong>Point</strong> 42 3.5 nH 4.0 pF 1.85 pF Z0 = 50 (see note) Transmission Line Output Under Test Device Pin (see note) NOTE: The data sheet provides timing at the device pin. For output timing analysis, the tester pin electronics and its transmission line effects must be taken into account. A transmission line with a delay of 2 ns or longer can be used to produce the desired transmission line effect. The transmission line is intended as a load only. It is not necessary to add or subtract the transmission line delay (2 ns or longer) from the data sheet timings. Input requirements in this data sheet are tested with an input slew rate of < 4 Volts per nanosecond (4 V/ns) at the device pin. Figure 25. Test Load Circuit for AC Timing Measurements signal transition levels All input and output timing parameters are referenced to 1.5 V for both “0” and “1” logic levels. Vref = 1.5 V Figure 26. Input and Output Voltage Reference Levels for AC Timing Measurements All rise and fall transition timing parameters are referenced to V IL MAX and V IH MIN for input clocks, V OL MAX and V OH MIN for output clocks. Vref = VIH MIN (or VOH MIN) Figure 27. Rise and Fall Transition Time Voltage Reference Levels Vref = VIL MAX (or VOL MAX) POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 101
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SPRS294A − OCTOBER 2005 − REVIS
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REVISION HISTORY SPRS294A − OCTOB
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GDP and ZDP 272-Ball BGA package (b
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functional block and CPU (DSP core)
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DEVICE CONFIGURATIONS (CONTINUED) p
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DEVICE CONFIGURATIONS (CONTINUED) S
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MULTIPLEXED PINS NAME PYP GDP/ ZDP
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configuration examples (continued)
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DEVICE CONFIGURATIONS (CONTINUED) S
Page 49 and 50: SIGNAL NAME PYP PIN NO. GDP/ ZDP TY
Page 51 and 52: SIGNAL NAME PYP PIN NO. GDP/ ZDP HD
Page 53 and 54: SIGNAL NAME PYP PIN NO. GDP/ ZDP ED
Page 55 and 56: SIGNAL NAME PYP PIN NO. GDP/ ZDP TY
Page 57 and 58: SIGNAL NAME PYP PIN NO. GDP/ ZDP SP
Page 59 and 60: SIGNAL NAME PYP PIN NO. GDP/ ZDP 11
Page 61 and 62: VSS SIGNAL NAME PYP PIN NO. GDP/ ZD
Page 63 and 64: VSS SIGNAL NAME PYP PIN NO. GDP/ ZD
Page 65 and 66: SPRS294A − OCTOBER 2005 − REVIS
Page 75 and 76: EDMA module and EDMA selector (cont
Page 77 and 78: PLL and PLL controller SPRS294A −
Page 85 and 86: multichannel audio serial port (McA
Page 87 and 88: multichannel audio serial port (McA
Page 99: SPRS294 − OCTOBER 2005 absolute m
Page 103 and 104: PARAMETER MEASUREMENT INFORMATION (
Page 105 and 106: INPUT AND OUTPUT CLOCKS SPRS294 −
Page 107 and 108: INPUT AND OUTPUT CLOCKS (CONTINUED)
Page 109 and 110: ASYNCHRONOUS MEMORY TIMING (CONTINU
Page 111 and 112: SYNCHRONOUS-BURST MEMORY TIMING tim
Page 113 and 114: SYNCHRONOUS DRAM TIMING timing requ
Page 115 and 116: SYNCHRONOUS DRAM TIMING (CONTINUED)
Page 117 and 118: SYNCHRONOUS DRAM TIMING (CONTINUED)
Page 119 and 120: HOLD/HOLDA TIMING SPRS294 − OCTOB
Page 121 and 122: timing requirements for reset †
Page 123 and 124: EXTERNAL INTERRUPT TIMING SPRS294
Page 125 and 126: MULTICHANNEL AUDIO SERIAL PORT (McA
Page 127 and 128: INTER-INTEGRATED CIRCUITS (I2C) TIM
Page 129 and 130: HOST-PORT INTERFACE TIMING SPRS294
Page 131 and 132: HOST-PORT INTERFACE TIMING (CONTINU
Page 133 and 134: MULTICHANNEL BUFFERED SERIAL PORT T
Page 139 and 140: SPRS294 − OCTOBER 2005 switching
Page 143 and 144: GENERAL-PURPOSE INPUT/OUTPUT (GPIO)
Page 145 and 146: MECHANICAL DATA SPRS294 − OCTOBER
Page 147 and 148: SPRS294 − OCTOBER 2005 packaging
Page 149 and 150: MECHANICAL DATA MPBG274 - MAY 2002
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IMPORTANT NOTICE Texas Instruments
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TMS320C6713B Floating-Point Digital Signal Processor (Rev. A)

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