TMS320C6713B Floating-Point Digital Signal Processor (Rev. A)

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SPRS294 − OCTOBER 2005 ASYNCHRONOUS MEMORY TIMING timing requirements for asynchronous memory cycles †‡§ (see Figure 36−Figure 37) NO. PYP-200,-225 GDP/ZDP -225, -300 PYPA −167, -200 UNIT GDPA/ZDPA −200 MIN MAX 3 tsu(EDV-AREH) Setup time, EDx valid before ARE high 6.5 ns 4 th(AREH-EDV) Hold time, EDx valid after ARE high 1 ns 6 tsu(ARDY-EKOH) Setup time, ARDY valid before ECLKOUT high 3 ns 7 th(EKOH-ARDY) Hold time, ARDY valid after ECLKOUT high 2.3 ns † To ensure data setup time, simply program the strobe width wide enough. ARDY is internally synchronized. The ARDY signal is recognized in the cycle for which the setup and hold time is met. To use ARDY as an asynchronous input, the pulse width of the ARDY signal should be wide enough (e.g., pulse width = 2E) to ensure setup and hold time is met. ‡ RS = Read setup, RST = Read strobe, RH = Read hold, WS = Write setup, WST = Write strobe, WH = Write hold. These parameters are programmed via the EMIF CE space control registers. § E = ECLKOUT period in ns switching characteristics over recommended operating conditions for asynchronous memory cycles ‡§ (see Figure 36−Figure 37) NO. PARAMETER PYP-200,-225 GDP/ZDP -225, -300 PYPA -167, -200 UNIT GDPA/ZDPA −200 MIN MAX 1 tosu(SELV-AREL) Output setup time, select signals valid to ARE low RS*E − 1.7 ns 2 toh(AREH-SELIV) Output hold time, ARE high to select signals invalid RH*E − 1.7 ns 5 td(EKOH-AREV) Delay time, ECLKOUT high to ARE valid 1.5 7 ns 8 tosu(SELV-AWEL) Output setup time, select signals valid to AWE low WS*E − 1.7 ns 9 toh(AWEH-SELIV) Output hold time, AWE high to select signals and EDx invalid WH*E − 1.7 ns 10 td(EKOH-AWEV) Delay time, ECLKOUT high to AWE valid 1.5 7 ns 11 tosu(EDV-AWEL) Output setup time, ED valid to AWE low (WS−1)*E − 1.7 ‡ RS = Read setup, RST = Read strobe, RH = Read hold, WS = Write setup, WST = Write strobe, WH = Write hold. These parameters are programmed via the EMIF CE space control registers. § E = ECLKOUT period in ns Select signals include: CEx, BE[3:0], EA[21:2], and AOE. ns 108 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
ASYNCHRONOUS MEMORY TIMING (CONTINUED) Setup = 2 Strobe = 3 Not Ready Hold = 2 SPRS294 − OCTOBER 2005 ECLKOUT CEx 1 2 BE[3:0] 1 BE 2 EA[21:2] 1 Address 2 ED[31:0] 3 4 AOE/SDRAS/SSOE† ARE/SDCAS/SSADS† 1 5 Read Data 2 5 AWE/SDWE/SSWE† ARDY 6 7 7 6 † AOE/SDRAS/SSOE, ARE/SDCAS/SSADS, and AWE/SDWE/SSWE operate as AOE (identified under select signals), ARE, and AWE, respectively, during asynchronous memory accesses. Figure 36. Asynchronous Memory Read Timing POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 109
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SPRS294A − OCTOBER 2005 − REVIS
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REVISION HISTORY SPRS294A − OCTOB
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GDP and ZDP 272-Ball BGA package (b
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functional block and CPU (DSP core)
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DEVICE CONFIGURATIONS (CONTINUED) p
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DEVICE CONFIGURATIONS (CONTINUED) S
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MULTIPLEXED PINS NAME PYP GDP/ ZDP
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configuration examples (continued)
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DEVICE CONFIGURATIONS (CONTINUED) S
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SIGNAL NAME PYP PIN NO. GDP/ ZDP TY
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SIGNAL NAME PYP PIN NO. GDP/ ZDP HD
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SIGNAL NAME PYP PIN NO. GDP/ ZDP ED
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SIGNAL NAME PYP PIN NO. GDP/ ZDP TY
Page 57 and 58: SIGNAL NAME PYP PIN NO. GDP/ ZDP SP
Page 59 and 60: SIGNAL NAME PYP PIN NO. GDP/ ZDP 11
Page 61 and 62: VSS SIGNAL NAME PYP PIN NO. GDP/ ZD
Page 63 and 64: VSS SIGNAL NAME PYP PIN NO. GDP/ ZD
Page 65 and 66: SPRS294A − OCTOBER 2005 − REVIS
Page 75 and 76: EDMA module and EDMA selector (cont
Page 77 and 78: PLL and PLL controller SPRS294A −
Page 85 and 86: multichannel audio serial port (McA
Page 87 and 88: multichannel audio serial port (McA
Page 99 and 100: SPRS294 − OCTOBER 2005 absolute m
Page 101 and 102: PARAMETER MEASUREMENT INFORMATION S
Page 103 and 104: PARAMETER MEASUREMENT INFORMATION (
Page 105 and 106: INPUT AND OUTPUT CLOCKS SPRS294 −
Page 107: INPUT AND OUTPUT CLOCKS (CONTINUED)
Page 111 and 112: SYNCHRONOUS-BURST MEMORY TIMING tim
Page 113 and 114: SYNCHRONOUS DRAM TIMING timing requ
Page 115 and 116: SYNCHRONOUS DRAM TIMING (CONTINUED)
Page 117 and 118: SYNCHRONOUS DRAM TIMING (CONTINUED)
Page 119 and 120: HOLD/HOLDA TIMING SPRS294 − OCTOB
Page 121 and 122: timing requirements for reset †
Page 123 and 124: EXTERNAL INTERRUPT TIMING SPRS294
Page 125 and 126: MULTICHANNEL AUDIO SERIAL PORT (McA
Page 127 and 128: INTER-INTEGRATED CIRCUITS (I2C) TIM
Page 129 and 130: HOST-PORT INTERFACE TIMING SPRS294
Page 131 and 132: HOST-PORT INTERFACE TIMING (CONTINU
Page 133 and 134: MULTICHANNEL BUFFERED SERIAL PORT T
Page 139 and 140: SPRS294 − OCTOBER 2005 switching
Page 143 and 144: GENERAL-PURPOSE INPUT/OUTPUT (GPIO)
Page 145 and 146: MECHANICAL DATA SPRS294 − OCTOBER
Page 147 and 148: SPRS294 − OCTOBER 2005 packaging
Page 149 and 150: MECHANICAL DATA MPBG274 - MAY 2002
Page 152: IMPORTANT NOTICE Texas Instruments
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TMS320C6713B Floating-Point Digital Signal Processor (Rev. A)

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