TMS320C6713B Floating-Point Digital Signal Processor (Rev. A)

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SPRS294 − OCTOBER 2005 SYNCHRONOUS DRAM TIMING (CONTINUED) MRS ECLKOUT CEx BE[3:0] EA[21:2] ED[31:0] AOE/SDRAS/SSOE† ARE/SDCAS/SSADS† AWE/SDWE/SSWE† 1 4 MRS value 12 8 11 1 5 12 8 11 † ARE/SDCAS/SSADS, AWE/SDWE/SSWE, and AOE/SDRAS/SSOE operate as SDCAS, SDWE, and SDRAS, respectively, during SDRAM accesses. Figure 46. SDRAM MRS Command 118 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
HOLD/HOLDA TIMING SPRS294 − OCTOBER 2005 timing requirements for the HOLD/HOLDA cycles † (see Figure 47) NO. PYP-200,-225 GDP/ZDP -225, -300 PYPA -167, -200 GDPA/ZDPA −200 UNIT MIN MAX 3 th(HOLDAL-HOLDL) Hold time, HOLD low after HOLDA low E ns † E = ECLKOUT period in ns switching characteristics over recommended operating conditions for the HOLD/HOLDA cycles †‡ (see Figure 47) NO. PARAMETER PYP-200,-225 GDP/ZDP -225, -300 PYPA -167, -200 GDPA/ZDPA −200 UNIT MIN MAX 1 td(HOLDL-EMHZ) Delay time, HOLD low to EMIF Bus high impedance 2E § ns 2 td(EMHZ-HOLDAL) Delay time, EMIF Bus high impedance to HOLDA low 0 2E ns 4 td(HOLDH-EMLZ) Delay time, HOLD high to EMIF Bus low impedance 2E 7E ns 5 td(EMLZ-HOLDAH) Delay time, EMIF Bus low impedance to HOLDA high 0 2E ns † E = ECLKOUT period in ns ‡ EMIF Bus consists of CE[3:0], BE[3:0], ED[31:0], EA[21:2], ARE/SDCAS/SSADS, AOE/SDRAS/SSOE, and AWE/SDWE/SSWE. § All pending EMIF transactions are allowed to complete before HOLDA is asserted. If no bus transactions are occurring, then the minimum delay time can be achieved. Also, bus hold can be indefinitely delayed by setting NOHOLD = 1. DSP Owns Bus External Requestor Owns Bus DSP Owns Bus 3 HOLD HOLDA 2 5 EMIF Bus† C6713B 1 4 C6713B † EMIF Bus consists of CE[3:0], BE[3:0], ED[31:0], EA[21:2], ARE/SDCAS/SSADS, AOE/SDRAS/SSOE, and AWE/SDWE/SSWE. Figure 47. HOLD/HOLDA Timing POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 119
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SPRS294A − OCTOBER 2005 − REVIS
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REVISION HISTORY SPRS294A − OCTOB
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GDP and ZDP 272-Ball BGA package (b
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functional block and CPU (DSP core)
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DEVICE CONFIGURATIONS (CONTINUED) p
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DEVICE CONFIGURATIONS (CONTINUED) S
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MULTIPLEXED PINS NAME PYP GDP/ ZDP
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configuration examples (continued)
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DEVICE CONFIGURATIONS (CONTINUED) S
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SIGNAL NAME PYP PIN NO. GDP/ ZDP TY
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SIGNAL NAME PYP PIN NO. GDP/ ZDP HD
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SIGNAL NAME PYP PIN NO. GDP/ ZDP ED
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SIGNAL NAME PYP PIN NO. GDP/ ZDP TY
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SIGNAL NAME PYP PIN NO. GDP/ ZDP SP
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SIGNAL NAME PYP PIN NO. GDP/ ZDP 11
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VSS SIGNAL NAME PYP PIN NO. GDP/ ZD
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VSS SIGNAL NAME PYP PIN NO. GDP/ ZD
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Page 67 and 68: SPRS294A − OCTOBER 2005 − REVIS
Page 75 and 76: EDMA module and EDMA selector (cont
Page 77 and 78: PLL and PLL controller SPRS294A −
Page 85 and 86: multichannel audio serial port (McA
Page 87 and 88: multichannel audio serial port (McA
Page 99 and 100: SPRS294 − OCTOBER 2005 absolute m
Page 101 and 102: PARAMETER MEASUREMENT INFORMATION S
Page 103 and 104: PARAMETER MEASUREMENT INFORMATION (
Page 105 and 106: INPUT AND OUTPUT CLOCKS SPRS294 −
Page 107 and 108: INPUT AND OUTPUT CLOCKS (CONTINUED)
Page 109 and 110: ASYNCHRONOUS MEMORY TIMING (CONTINU
Page 111 and 112: SYNCHRONOUS-BURST MEMORY TIMING tim
Page 113 and 114: SYNCHRONOUS DRAM TIMING timing requ
Page 115 and 116: SYNCHRONOUS DRAM TIMING (CONTINUED)
Page 117: SYNCHRONOUS DRAM TIMING (CONTINUED)
Page 121 and 122: timing requirements for reset †
Page 123 and 124: EXTERNAL INTERRUPT TIMING SPRS294
Page 125 and 126: MULTICHANNEL AUDIO SERIAL PORT (McA
Page 127 and 128: INTER-INTEGRATED CIRCUITS (I2C) TIM
Page 129 and 130: HOST-PORT INTERFACE TIMING SPRS294
Page 131 and 132: HOST-PORT INTERFACE TIMING (CONTINU
Page 133 and 134: MULTICHANNEL BUFFERED SERIAL PORT T
Page 139 and 140: SPRS294 − OCTOBER 2005 switching
Page 143 and 144: GENERAL-PURPOSE INPUT/OUTPUT (GPIO)
Page 145 and 146: MECHANICAL DATA SPRS294 − OCTOBER
Page 147 and 148: SPRS294 − OCTOBER 2005 packaging
Page 149 and 150: MECHANICAL DATA MPBG274 - MAY 2002
Page 152: IMPORTANT NOTICE Texas Instruments
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TMS320C6713B Floating-Point Digital Signal Processor (Rev. A)

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