TMS320C6713B Floating-Point Digital Signal Processor (Rev. A)

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SPRS294A − OCTOBER 2005 − REVISED NOVEMBER 2005 device characteristics Table 2 provides an overview of the C6713B DSP. The table shows significant features of the device, including the capacity of on-chip RAM, the peripherals, the execution time, and the package type with pin count. For more details on the C67x DSP device part numbers and part numbering, see Figure 12. Table 2. Characteristics of the C6713B Processor HARDWARE FEATURES INTERNAL CLOCK SOURCE C6713B (FLOATING-POINT DSP) GDP/ZDP PYP Peripherals EMIF SYSCLK3 or ECLKIN 1 (32 bit) 1 (16 bit) EDMA (16 Channels) Not all peripheral pins are CPU clock frequency 1 available at the same HPI (16 bit) SYSCLK2 1 time. (For more details, McASPs AUXCLK, SYSCLK2† 2 see the Device Configurations section.) I2Cs SYSCLK2 2 McBSPs SYSCLK2 2 Peripheral performance is dependent on chip-level 32-Bit Timers 1/2 of SYSCLK2 2 configuration. GPIO Module SYSCLK2 1 Size (Bytes) 4K-Byte (4KB) L1 Program (L1P) Cache On-Chip Memory 4KB L1 Data (L1D) Cache Organization 64KB Unified L2 Cache/Mapped RAM 192KB L2 Mapped RAM CPU ID+CPU Rev ID Control Status Register (CSR.[31:16]) 0x0203 BSDL File For the C6713B BSDL file, contact your Field Sales Representative. Frequency MHz 300, 225, 200 225, 200, 167 Cycle Time ns 3.3 ns (GDP-300, ZDP-300) 4.4 ns (GDP-225, ZDP-225) 5 ns (GDPA-200, ZDPA-200) 264K 5 ns (PYP-200) 4.4 ns (PYP-225) 6 ns (PYPA−167) 5 ns (PYPA-200) 1.20‡ V Core (V) Voltage 1.4 V (−300) 1.2 V I/O (V) 3.3 V Clock Generator Options Prescaler Multiplier Postscaler /1, /2, /3, ..., /32 x4, x5, x6, ..., x25 /1, /2, /3, ..., /32 27 x 27 mm 272-Ball BGA (GDP) 272-Ball BGA (ZDP) − Packages 208-Pin PowerPAD 28 x 28 mm − PQFP (PYP) Process Technology µm 0.13 Product Status Product Preview (PP) PD§ Advance Information (AI) Production Data (PD) † AUXCLK is the McASP internal high-frequency clock source for serial transfers. SYSCLK2 is the McASP system clock used for the clock check (high-frequency) circuit. ‡ This value is compatible with existing 1.26-V designs. § PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. C67x is a trademark of Texas Instruments. 12 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
functional block and CPU (DSP core) diagram SPRS294A − OCTOBER 2005 − REVISED NOVEMBER 2005 Digital Signal Processor Pin Multiplexing 32 EMIF McASP1 McASP0 McBSP1 McBSP0 I2C1 I2C0 Timer 1 Enhanced DMA Controller (16 channel) L2 Cache/ Memory 4 Banks 64K Bytes Total (up to 4-Way) L2 Memory 192K Bytes L1P Cache Direct Mapped 4K Bytes Total Instruction Fetch Instruction Dispatch C67x CPU Instruction Decode Data Path A Data Path B A Register File B Register File .L1 † .S1 † .M1 † .D1 .D2 .M2 † .S2 † .L2 † L1D Cache 2-Way Set Associative 4K Bytes Control Registers Control Logic Test In-Circuit Emulation Interrupt Control Timer 0 Clock Generator and PLL x4 through x25 Multiplier /1 through /32 Dividers Power-Down Logic GPIO 16 HPI † In addition to fixed-point instructions, these functional units execute floating-point instructions. EMIF interfaces to: −SDRAM −SBSRAM −SRAM, −ROM/Flash, and −I/O devices McBSPs interface to: −SPI Control Port −High-Speed TDM Codecs −AC97 Codecs −Serial EEPROM McASPs interface to: −I2S Multichannel ADC, DAC, Codec, DIR −DIT: Multiple Outputs POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 13
Page 1 and 2: SPRS294A − OCTOBER 2005 − REVIS
Page 3 and 4: REVISION HISTORY SPRS294A − OCTOB
Page 5 and 6: GDP and ZDP 272-Ball BGA package (b
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Page 35 and 36: DEVICE CONFIGURATIONS (CONTINUED) p
Page 37 and 38: DEVICE CONFIGURATIONS (CONTINUED) S
Page 39 and 40: MULTIPLEXED PINS NAME PYP GDP/ ZDP
Page 41 and 42: configuration examples (continued)
Page 47 and 48: DEVICE CONFIGURATIONS (CONTINUED) S
Page 49 and 50: SIGNAL NAME PYP PIN NO. GDP/ ZDP TY
Page 51 and 52: SIGNAL NAME PYP PIN NO. GDP/ ZDP HD
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Page 61 and 62: VSS SIGNAL NAME PYP PIN NO. GDP/ ZD
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VSS SIGNAL NAME PYP PIN NO. GDP/ ZD
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SPRS294A − OCTOBER 2005 − REVIS
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EDMA module and EDMA selector (cont
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PLL and PLL controller SPRS294A −
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multichannel audio serial port (McA
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multichannel audio serial port (McA
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SPRS294 − OCTOBER 2005 absolute m
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PARAMETER MEASUREMENT INFORMATION S
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PARAMETER MEASUREMENT INFORMATION (
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INPUT AND OUTPUT CLOCKS SPRS294 −
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INPUT AND OUTPUT CLOCKS (CONTINUED)
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ASYNCHRONOUS MEMORY TIMING (CONTINU
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SYNCHRONOUS-BURST MEMORY TIMING tim
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SYNCHRONOUS DRAM TIMING timing requ
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SYNCHRONOUS DRAM TIMING (CONTINUED)
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SYNCHRONOUS DRAM TIMING (CONTINUED)
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HOLD/HOLDA TIMING SPRS294 − OCTOB
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timing requirements for reset †
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EXTERNAL INTERRUPT TIMING SPRS294
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MULTICHANNEL AUDIO SERIAL PORT (McA
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INTER-INTEGRATED CIRCUITS (I2C) TIM
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HOST-PORT INTERFACE TIMING SPRS294
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HOST-PORT INTERFACE TIMING (CONTINU
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MULTICHANNEL BUFFERED SERIAL PORT T
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SPRS294 − OCTOBER 2005 switching
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GENERAL-PURPOSE INPUT/OUTPUT (GPIO)
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MECHANICAL DATA SPRS294 − OCTOBER
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SPRS294 − OCTOBER 2005 packaging
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MECHANICAL DATA MPBG274 - MAY 2002
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IMPORTANT NOTICE Texas Instruments
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TMS320C6713B Floating-Point Digital Signal Processor (Rev. A)

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