TMS320C6713B Floating-Point Digital Signal Processor (Rev. A)

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SPRS294 − OCTOBER 2005 PARAMETER MEASUREMENT INFORMATION (CONTINUED) AC transient rise/fall time specifications Figure 28 and Figure 29 show the AC transient specifications for Rise and Fall Time. For device-specific information on these values, refer to the Recommended Operating Conditions section of this Data Sheet. t = 0.3 tc (max)† Minimum Risetime Waveform Valid Region VIH (min) VOS (max) Ground † tc = the peripheral cycle time. Figure 28. AC Transient Specification Rise Time t = 0.3 tc(max)† VIL (max) VUS (max) Ground † tc = the peripheral cycle time. Figure 29. AC Transient Specification Fall Time 102 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
PARAMETER MEASUREMENT INFORMATION (CONTINUED) timing parameters and board routing analysis SPRS294 − OCTOBER 2005 The timing parameter values specified in this data sheet do not include delays by board routings. As a good board design practice, such delays must always be taken into account. Timing values may be adjusted by increasing/decreasing such delays. TI recommends utilizing the available I/O buffer information specification (IBIS) models to analyze the timing characteristics correctly. To properly use IBIS models to attain accurate timing analysis for a given system, see the Using IBIS Models for Timing Analysis application report (literature number SPRA839). If needed, external logic hardware such as buffers may be used to compensate any timing differences. For inputs, timing is most impacted by the round-trip propagation delay from the DSP to the external device and from the external device to the DSP. This round-trip delay tends to negatively impact the input setup time margin, but also tends to improve the input hold time margins (see Table 46 and Figure 30). Figure 30 represents a general transfer between the DSP and an external device. The figure also represents board route delays and how they are perceived by the DSP and the external device. POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 103
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SPRS294A − OCTOBER 2005 − REVIS
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REVISION HISTORY SPRS294A − OCTOB
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GDP and ZDP 272-Ball BGA package (b
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functional block and CPU (DSP core)
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DEVICE CONFIGURATIONS (CONTINUED) p
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DEVICE CONFIGURATIONS (CONTINUED) S
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MULTIPLEXED PINS NAME PYP GDP/ ZDP
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configuration examples (continued)
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DEVICE CONFIGURATIONS (CONTINUED) S
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SIGNAL NAME PYP PIN NO. GDP/ ZDP TY
Page 51 and 52: SIGNAL NAME PYP PIN NO. GDP/ ZDP HD
Page 53 and 54: SIGNAL NAME PYP PIN NO. GDP/ ZDP ED
Page 55 and 56: SIGNAL NAME PYP PIN NO. GDP/ ZDP TY
Page 57 and 58: SIGNAL NAME PYP PIN NO. GDP/ ZDP SP
Page 59 and 60: SIGNAL NAME PYP PIN NO. GDP/ ZDP 11
Page 61 and 62: VSS SIGNAL NAME PYP PIN NO. GDP/ ZD
Page 63 and 64: VSS SIGNAL NAME PYP PIN NO. GDP/ ZD
Page 65 and 66: SPRS294A − OCTOBER 2005 − REVIS
Page 75 and 76: EDMA module and EDMA selector (cont
Page 77 and 78: PLL and PLL controller SPRS294A −
Page 85 and 86: multichannel audio serial port (McA
Page 87 and 88: multichannel audio serial port (McA
Page 99 and 100: SPRS294 − OCTOBER 2005 absolute m
Page 101: PARAMETER MEASUREMENT INFORMATION S
Page 105 and 106: INPUT AND OUTPUT CLOCKS SPRS294 −
Page 107 and 108: INPUT AND OUTPUT CLOCKS (CONTINUED)
Page 109 and 110: ASYNCHRONOUS MEMORY TIMING (CONTINU
Page 111 and 112: SYNCHRONOUS-BURST MEMORY TIMING tim
Page 113 and 114: SYNCHRONOUS DRAM TIMING timing requ
Page 115 and 116: SYNCHRONOUS DRAM TIMING (CONTINUED)
Page 117 and 118: SYNCHRONOUS DRAM TIMING (CONTINUED)
Page 119 and 120: HOLD/HOLDA TIMING SPRS294 − OCTOB
Page 121 and 122: timing requirements for reset †
Page 123 and 124: EXTERNAL INTERRUPT TIMING SPRS294
Page 125 and 126: MULTICHANNEL AUDIO SERIAL PORT (McA
Page 127 and 128: INTER-INTEGRATED CIRCUITS (I2C) TIM
Page 129 and 130: HOST-PORT INTERFACE TIMING SPRS294
Page 131 and 132: HOST-PORT INTERFACE TIMING (CONTINU
Page 133 and 134: MULTICHANNEL BUFFERED SERIAL PORT T
Page 139 and 140: SPRS294 − OCTOBER 2005 switching
Page 143 and 144: GENERAL-PURPOSE INPUT/OUTPUT (GPIO)
Page 145 and 146: MECHANICAL DATA SPRS294 − OCTOBER
Page 147 and 148: SPRS294 − OCTOBER 2005 packaging
Page 149 and 150: MECHANICAL DATA MPBG274 - MAY 2002
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IMPORTANT NOTICE Texas Instruments
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TMS320C6713B Floating-Point Digital Signal Processor (Rev. A)

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