TMS320C6713B Floating-Point Digital Signal Processor (Rev. A)

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SPRS294 − OCTOBER 2005 MULTICHANNEL AUDIO SERIAL PORT (McASP) TIMING timing requirements for McASP (see Figure 51 and Figure 52) NO. PYP-200,-225 GDP/ZDP -225, -300 PYPA -167, -200 UNIT GDPA/ZDPA −200 MIN MAX 1 tc(AHCKRX) Cycle time, AHCLKR/X 20 ns 2 tw(AHCKRX) Pulse duration, AHCLKR/X high or low 7.5 ns 3 tc(ACKRX) Cycle time, ACLKR/X ACLKR/X ext greater of 2P or 33 ns† 4 tw(ACKRX) Pulse duration, ACLKR/X high or low ACLKR/X ext 14 ns 5 tsu(AFRXC-ACKRX) 6 th(ACKRX-AFRX) 7 tsu(AXR-ACKRX) Setup time, AFSR/X input valid before ACLKR/X latches ACLKR/X int 6 ns data ACLKR/X ext 3 ns Hold time, AFSR/X input valid after ACLKR/X latches ACLKR/X int 0 ns data ACLKR/X ext 3 ns Setup time, AXR input valid before ACLKR/X latches ACLKR/X int 8 ns data ACLKR/X ext 3 ns 8 th(ACKRX-AXR) Hold time, AXR input valid after ACLKR/X latches data † P = SYSCLK2 period. ACLKR/X int 1 ns ACLKR/X ext 3 ns switching characteristics over recommended operating conditions for McASP ‡ (see Figure 51 and Figure 52) NO. PARAMETER PYP-200,-225 GDP/ZDP -225, -300 PYPA -167, -200 UNIT GDPA/ZDPA −200 MIN MAX 9 tc(AHCKRX) Cycle time, AHCLKR/X 20 ns 10 tw(AHCKRX) Pulse duration, AHCLKR/X high or low (AH/2) − 2.5 ns 11 tc(ACKRX) Cycle time, ACLKR/X ACLKR/X int greater of 2P or 33 ns† 12 tw(ACKRX) Pulse duration, ACLKR/X high or low ACLKR/X int (A/2) − 2.5 ns 13 td(ACKRX-AFRX) Delay time, ACLKR/X transmit edge to AFSX/R output ACLKR/X int −1 5 ns valid ACLKR/X ext 0 10 ns 14 td(ACKX-AXRV) Delay time, ACLKX transmit edge to AXR output valid 15 tdis(ACKRX−AXRHZ) † P = SYSCLK2 period. ‡ AH = AHCLKR/X period in ns. A = ACLKR/X period in ns. ns ns ACLKR/X int −1 5 ns ACLKR/X ext 0 10 ns Disable time, AXR high impedance following last data bit ACLKR/X int −1 10 ns from ACLKR/X transmit edge ACLKR/X ext −1 10 ns 124 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
MULTICHANNEL AUDIO SERIAL PORT (McASP) TIMING (CONTINUED) SPRS294 − OCTOBER 2005 AHCLKR/X (Falling Edge Polarity) 1 2 2 AHCLKR/X (Rising Edge Polarity) ACLKR/X (CLKRP = CLKXP = 0)† 3 4 4 ACLKR/X (CLKRP = CLKXP = 1)‡ AFSR/X (Bit Width, 0 Bit Delay) 6 5 AFSR/X (Bit Width, 1 Bit Delay) AFSR/X (Bit Width, 2 Bit Delay) AFSR/X (Slot Width, 0 Bit Delay) AFSR/X (Slot Width, 1 Bit Delay) AFSR/X (Slot Width, 2 Bit Delay) AXR[n] (Data In/Receive) 8 7 A0 A1 A30 A31 B0 B1 B30 B31 C0 C1 C2 C3 C31 † For CLKRP = CLKXP = 0, the McASP transmitter is configured for rising edge (to shift data out) and the McASP receiver is configured for falling edge (to shift data in). ‡ For CLKRP = CLKXP = 1, the McASP transmitter is configured for falling edge (to shift data out) and the McASP receiver is configured for rising edge (to shift data in). Figure 51. McASP Input Timings POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 125
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SPRS294A − OCTOBER 2005 − REVIS
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REVISION HISTORY SPRS294A − OCTOB
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GDP and ZDP 272-Ball BGA package (b
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functional block and CPU (DSP core)
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DEVICE CONFIGURATIONS (CONTINUED) p
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DEVICE CONFIGURATIONS (CONTINUED) S
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MULTIPLEXED PINS NAME PYP GDP/ ZDP
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configuration examples (continued)
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DEVICE CONFIGURATIONS (CONTINUED) S
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SIGNAL NAME PYP PIN NO. GDP/ ZDP TY
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SIGNAL NAME PYP PIN NO. GDP/ ZDP HD
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SIGNAL NAME PYP PIN NO. GDP/ ZDP ED
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SIGNAL NAME PYP PIN NO. GDP/ ZDP TY
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SIGNAL NAME PYP PIN NO. GDP/ ZDP SP
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SIGNAL NAME PYP PIN NO. GDP/ ZDP 11
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VSS SIGNAL NAME PYP PIN NO. GDP/ ZD
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VSS SIGNAL NAME PYP PIN NO. GDP/ ZD
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Page 73 and 74: SPRS294A − OCTOBER 2005 − REVIS
Page 75 and 76: EDMA module and EDMA selector (cont
Page 77 and 78: PLL and PLL controller SPRS294A −
Page 85 and 86: multichannel audio serial port (McA
Page 87 and 88: multichannel audio serial port (McA
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Page 105 and 106: INPUT AND OUTPUT CLOCKS SPRS294 −
Page 107 and 108: INPUT AND OUTPUT CLOCKS (CONTINUED)
Page 109 and 110: ASYNCHRONOUS MEMORY TIMING (CONTINU
Page 111 and 112: SYNCHRONOUS-BURST MEMORY TIMING tim
Page 113 and 114: SYNCHRONOUS DRAM TIMING timing requ
Page 115 and 116: SYNCHRONOUS DRAM TIMING (CONTINUED)
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Page 119 and 120: HOLD/HOLDA TIMING SPRS294 − OCTOB
Page 121 and 122: timing requirements for reset †
Page 123: EXTERNAL INTERRUPT TIMING SPRS294
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Page 129 and 130: HOST-PORT INTERFACE TIMING SPRS294
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Page 133 and 134: MULTICHANNEL BUFFERED SERIAL PORT T
Page 139 and 140: SPRS294 − OCTOBER 2005 switching
Page 143 and 144: GENERAL-PURPOSE INPUT/OUTPUT (GPIO)
Page 145 and 146: MECHANICAL DATA SPRS294 − OCTOBER
Page 147 and 148: SPRS294 − OCTOBER 2005 packaging
Page 149 and 150: MECHANICAL DATA MPBG274 - MAY 2002
Page 152: IMPORTANT NOTICE Texas Instruments
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TMS320C6713B Floating-Point Digital Signal Processor (Rev. A)

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