TMS320C6713B Floating-Point Digital Signal Processor (Rev. A)

More documents

Recommendations

Info

SPRS294A − OCTOBER 2005 − REVISED NOVEMBER 2005 multichannel audio serial port (McASP) peripherals The device includes two multi-channel audio serial port (McASP) interface peripherals (McASP1 and McASP0). The McASP is a serial port optimized for the needs of multi-channel audio applications. With two McASP peripherals, the device is capable of supporting two completely independent audio zones simultaneously. Each McASP consists of a transmit and receive section. These sections can operate completely independently with different data formats, separate master clocks, bit clocks, and frame syncs or alternatively, the transmit and receive sections may be synchronized. Each McASP module also includes a pool of 16 shift registers that may be configured to operate as either transmit data, receive data, or general-purpose I/O (GPIO). The transmit section of the McASP can transmit data in either a time-division-multiplexed (TDM) synchronous serial format or in a digital audio interface (DIT) format where the bit stream is encoded for S/PDIF, AES-3, IEC-60958, CP-430 transmission. The receive section of the McASP supports the TDM synchronous serial format. Each McASP can support one transmit data format (either a TDM format or DIT format) and one receive format at a time. All transmit shift registers use the same format and all receive shift registers use the same format. However, the transmit and receive formats need not be the same. Both the transmit and receive sections of the McASP also support burst mode which is useful for non-audio data (for example, passing control information between two DSPs). The McASP peripherals have additional capability for flexible clock generation, and error detection/handling, as well as error management. McASP block diagram Figure 16 illustrates the major blocks along with external signals of the McASP1 and McASP0 peripherals; and shows the 8 serial data [AXR] pins for each McASP. Each McASP also includes full general-purpose I/O (GPIO) control, so any pins not needed for serial transfers can be used for general-purpose I/O. 84 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
multichannel audio serial port (McASP) peripherals (continued) SPRS294A − OCTOBER 2005 − REVISED NOVEMBER 2005 McASP0 McASP1 DIT RAM Transmit Frame Sync Generator AFSX0 DIT RAM Transmit Frame Sync Generator AFSX1 Transmit Clock Check (High- Frequency) Transmit Clock Generator AHCLKX0 ACLKX0 Transmit Clock Check (High- Frequency) Transmit Clock Generator AHCLKX1 ACLKX1 Error Detect AMUTE0 AMUTEIN0 Error Detect AMUTE1 AMUTEIN1 Receive Clock Check (High- Frequency) Receive Clock Generator AHCLKR0 ACLKR0 Receive Clock Check (High- Frequency) Receive Clock Generator AHCLKR1 ACLKR1 DMA Transmit Transmit Data Formatter Receive Frame Sync Generator AFSR0 DMA Transmit Transmit Data Formatter Receive Frame Sync Generator AFSR1 INDIVIDUALLY PROGRAMMABLE TX/RX/GPIO Serializer 0 Serializer 1 Serializer 2 Serializer 3 Serializer 4 Serializer 5 Serializer 6 Serializer 7 AXR0[0] AXR0[1] AXR0[2] AXR0[3] AXR0[4] AXR0[5] AXR0[6] AXR0[7] INDIVIDUALLY PROGRAMMABLE TX/RX/GPIO Serializer 0 Serializer 1 Serializer 2 Serializer 3 Serializer 4 Serializer 5 Serializer 6 Serializer 7 AXR1[0] AXR1[1] AXR1[2] AXR1[3] AXR1[4] AXR1[5] AXR1[6] AXR1[7] DMA Receive Receive Data Formatter GPIO Control DMA Receive Receive Data Formatter GPIO Control Figure 16. McASP0 and McASP1 Configuration POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 85
Page 1 and 2:
SPRS294A − OCTOBER 2005 − REVIS
Page 3 and 4:
REVISION HISTORY SPRS294A − OCTOB
Page 5 and 6:
GDP and ZDP 272-Ball BGA package (b
Page 7 and 8:
Page 9 and 10:
Page 11 and 12:
Page 13 and 14:
functional block and CPU (DSP core)
Page 15 and 16:
Á Á Á Á Á Á ÁÁÁÁÁ ÁÁÁ
Page 17 and 18:
Page 19 and 20:
Page 21 and 22:
Page 23 and 24:
Page 25 and 26:
Page 27 and 28:
Page 29 and 30:
Page 31 and 32:
Page 33 and 34: SPRS294A − OCTOBER 2005 − REVIS
Page 35 and 36: DEVICE CONFIGURATIONS (CONTINUED) p
Page 37 and 38: DEVICE CONFIGURATIONS (CONTINUED) S
Page 39 and 40: MULTIPLEXED PINS NAME PYP GDP/ ZDP
Page 41 and 42: configuration examples (continued)
Page 47 and 48: DEVICE CONFIGURATIONS (CONTINUED) S
Page 49 and 50: SIGNAL NAME PYP PIN NO. GDP/ ZDP TY
Page 51 and 52: SIGNAL NAME PYP PIN NO. GDP/ ZDP HD
Page 53 and 54: SIGNAL NAME PYP PIN NO. GDP/ ZDP ED
Page 55 and 56: SIGNAL NAME PYP PIN NO. GDP/ ZDP TY
Page 57 and 58: SIGNAL NAME PYP PIN NO. GDP/ ZDP SP
Page 59 and 60: SIGNAL NAME PYP PIN NO. GDP/ ZDP 11
Page 61 and 62: VSS SIGNAL NAME PYP PIN NO. GDP/ ZD
Page 63 and 64: VSS SIGNAL NAME PYP PIN NO. GDP/ ZD
Page 75 and 76: EDMA module and EDMA selector (cont
Page 77 and 78: PLL and PLL controller SPRS294A −
Page 83: SPRS294A − OCTOBER 2005 − REVIS
Page 87 and 88: multichannel audio serial port (McA
Page 99 and 100: SPRS294 − OCTOBER 2005 absolute m
Page 101 and 102: PARAMETER MEASUREMENT INFORMATION S
Page 103 and 104: PARAMETER MEASUREMENT INFORMATION (
Page 105 and 106: INPUT AND OUTPUT CLOCKS SPRS294 −
Page 107 and 108: INPUT AND OUTPUT CLOCKS (CONTINUED)
Page 109 and 110: ASYNCHRONOUS MEMORY TIMING (CONTINU
Page 111 and 112: SYNCHRONOUS-BURST MEMORY TIMING tim
Page 113 and 114: SYNCHRONOUS DRAM TIMING timing requ
Page 115 and 116: SYNCHRONOUS DRAM TIMING (CONTINUED)
Page 117 and 118: SYNCHRONOUS DRAM TIMING (CONTINUED)
Page 119 and 120: HOLD/HOLDA TIMING SPRS294 − OCTOB
Page 121 and 122: timing requirements for reset †
Page 123 and 124: EXTERNAL INTERRUPT TIMING SPRS294
Page 125 and 126: MULTICHANNEL AUDIO SERIAL PORT (McA
Page 127 and 128: INTER-INTEGRATED CIRCUITS (I2C) TIM
Page 129 and 130: HOST-PORT INTERFACE TIMING SPRS294
Page 131 and 132: HOST-PORT INTERFACE TIMING (CONTINU
Page 133 and 134: MULTICHANNEL BUFFERED SERIAL PORT T
Page 135 and 136:
MULTICHANNEL BUFFERED SERIAL PORT T
Page 137 and 138:
Page 139 and 140:
SPRS294 − OCTOBER 2005 switching
Page 141 and 142:
Page 143 and 144:
GENERAL-PURPOSE INPUT/OUTPUT (GPIO)
Page 145 and 146:
MECHANICAL DATA SPRS294 − OCTOBER
Page 147 and 148:
SPRS294 − OCTOBER 2005 packaging
Page 149 and 150:
MECHANICAL DATA MPBG274 - MAY 2002
Page 152:
IMPORTANT NOTICE Texas Instruments
show all

TMS320C6713B Floating-Point Digital Signal Processor (Rev. A)

You also want an ePaper? Increase the reach of your titles

Delete template?

Save as template?