TMS320C6713B Floating-Point Digital Signal Processor (Rev. A)

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SPRS294 − OCTOBER 2005 MULTICHANNEL BUFFERED SERIAL PORT TIMING (CONTINUED) CLKX FSX 1 2 DX DR 6 7 3 Bit 0 Bit(n-1) (n-2) (n-3) (n-4) 4 5 Bit 0 Bit(n-1) (n-2) (n-3) (n-4) Figure 62. McBSP Timing as SPI Master or Slave: CLKSTP = 11b, CLKXP = 0 timing requirements for McBSP as SPI master or slave: CLKSTP = 10b, CLKXP = 1 †‡ (see Figure 63) NO. PYP-200,-225 GDP/ZDP -225, -300 PYPA -167, -200 GDPA/ZDPA −200 UNIT MASTER SLAVE MIN MAX MIN MAX 4 tsu(DRV-CKXH) Setup time, DR valid before CLKX high 12 2 − 6P ns 5 th(CKXH-DRV) Hold time, DR valid after CLKX high 4 5 + 12P ns † P = 1/CPU clock frequency in ns. For example, when running parts at 300 MHz, use P = 3.3 ns. ‡ For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1. 138 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
SPRS294 − OCTOBER 2005 switching characteristics over recommended operating conditions for McBSP as SPI master or slave: CLKSTP = 10b, CLKXP = 1 †‡ (see Figure 63) NO. PARAMETER PYP-200,-225 GDP/ZDP -225, -300 PYPA -167, -200 GDPA/ZDPA −200 MASTER§ SLAVE MIN MAX MIN MAX 1 th(CKXH-FXL) Hold time, FSX low after CLKX high T − 2 T + 3 ns 2 td(FXL-CKXL) Delay time, FSX low to CLKX low# H − 2 H + 3 ns 3 td(CKXL-DXV) Delay time, CLKX low to DX valid −3 4 6P + 2 10P + 17 ns 6 tdis(CKXH-DXHZ) Disable time, DX high impedance following last data bit from CLKX high UNIT H − 2 H + 3 ns 7 tdis(FXH-DXHZ) Disable time, DX high impedance following last data bit from FSX high 2P + 3 6P + 17 ns 8 td(FXL-DXV) Delay time, FSX low to DX valid 4P + 2 8P + 17 ns † P = 1/CPU clock frequency in ns. For example, when running parts at 300 MHz, use P = 3.3 ns. ‡ For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1. § S = Sample rate generator input clock = 2P if CLKSM = 1 (P = 1/CPU clock frequency) = Sample rate generator input clock = P_clks if CLKSM = 0 (P_clks = CLKS period) T = CLKX period = (1 + CLKGDV) * S H = CLKX high pulse width = (CLKGDV/2 + 1) * S if CLKGDV is even = (CLKGDV + 1)/2 * S if CLKGDV is odd or zero L = CLKX low pulse width = (CLKGDV/2) * S if CLKGDV is even = (CLKGDV + 1)/2 * S if CLKGDV is odd or zero FSRP = FSXP = 1. As a SPI master, FSX is inverted to provide active-low slave-enable output. As a slave, the active-low signal input on FSX and FSR is inverted before being used internally. CLKXM = FSXM = 1, CLKRM = FSRM = 0 for master McBSP CLKXM = CLKRM = FSXM = FSRM = 0 for slave McBSP # FSX should be low before the rising edge of clock to enable slave devices and then begin a SPI transfer at the rising edge of the master clock (CLKX). CLKX FSX DX DR 1 6 2 7 8 3 Bit 0 Bit(n-1) (n-2) (n-3) (n-4) 4 5 Bit 0 Bit(n-1) (n-2) (n-3) (n-4) Figure 63. McBSP Timing as SPI Master or Slave: CLKSTP = 10b, CLKXP = 1 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 139
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SPRS294A − OCTOBER 2005 − REVIS
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REVISION HISTORY SPRS294A − OCTOB
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GDP and ZDP 272-Ball BGA package (b
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functional block and CPU (DSP core)
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DEVICE CONFIGURATIONS (CONTINUED) p
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DEVICE CONFIGURATIONS (CONTINUED) S
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MULTIPLEXED PINS NAME PYP GDP/ ZDP
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configuration examples (continued)
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DEVICE CONFIGURATIONS (CONTINUED) S
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SIGNAL NAME PYP PIN NO. GDP/ ZDP TY
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SIGNAL NAME PYP PIN NO. GDP/ ZDP HD
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SIGNAL NAME PYP PIN NO. GDP/ ZDP ED
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SIGNAL NAME PYP PIN NO. GDP/ ZDP TY
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SIGNAL NAME PYP PIN NO. GDP/ ZDP SP
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SIGNAL NAME PYP PIN NO. GDP/ ZDP 11
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VSS SIGNAL NAME PYP PIN NO. GDP/ ZD
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VSS SIGNAL NAME PYP PIN NO. GDP/ ZD
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EDMA module and EDMA selector (cont
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PLL and PLL controller SPRS294A −
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multichannel audio serial port (McA
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Page 89 and 90: SPRS294A − OCTOBER 2005 − REVIS
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Page 101 and 102: PARAMETER MEASUREMENT INFORMATION S
Page 103 and 104: PARAMETER MEASUREMENT INFORMATION (
Page 105 and 106: INPUT AND OUTPUT CLOCKS SPRS294 −
Page 107 and 108: INPUT AND OUTPUT CLOCKS (CONTINUED)
Page 109 and 110: ASYNCHRONOUS MEMORY TIMING (CONTINU
Page 111 and 112: SYNCHRONOUS-BURST MEMORY TIMING tim
Page 113 and 114: SYNCHRONOUS DRAM TIMING timing requ
Page 115 and 116: SYNCHRONOUS DRAM TIMING (CONTINUED)
Page 117 and 118: SYNCHRONOUS DRAM TIMING (CONTINUED)
Page 119 and 120: HOLD/HOLDA TIMING SPRS294 − OCTOB
Page 121 and 122: timing requirements for reset †
Page 123 and 124: EXTERNAL INTERRUPT TIMING SPRS294
Page 125 and 126: MULTICHANNEL AUDIO SERIAL PORT (McA
Page 127 and 128: INTER-INTEGRATED CIRCUITS (I2C) TIM
Page 129 and 130: HOST-PORT INTERFACE TIMING SPRS294
Page 131 and 132: HOST-PORT INTERFACE TIMING (CONTINU
Page 133 and 134: MULTICHANNEL BUFFERED SERIAL PORT T
Page 137: MULTICHANNEL BUFFERED SERIAL PORT T
Page 143 and 144: GENERAL-PURPOSE INPUT/OUTPUT (GPIO)
Page 145 and 146: MECHANICAL DATA SPRS294 − OCTOBER
Page 147 and 148: SPRS294 − OCTOBER 2005 packaging
Page 149 and 150: MECHANICAL DATA MPBG274 - MAY 2002
Page 152: IMPORTANT NOTICE Texas Instruments
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TMS320C6713B Floating-Point Digital Signal Processor (Rev. A)

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