TMS320C6713B Floating-Point Digital Signal Processor (Rev. A)

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SPRS294A − OCTOBER 2005 − REVISED NOVEMBER 2005 SIGNAL NAME PYP PIN NO. GDP/ ZDP TYPE† Terminal Functions (Continued) IPD/ IPU‡ DESCRIPTION EMIF − ASYNCHRONOUS/SYNCHRONOUS MEMORY CONTROL ECLKIN 78 Y11 I IPD External EMIF input clock source ECLKOUT 77 Y10 O/Z IPD ARE/SDCAS/ SSADS AOE/SDRAS/ SSOE AWE/SDWE/ SSWE 79 V11 O/Z IPU 75 W10 O/Z IPU 83 V12 O/Z IPU ARDY 56 Y5 I IPU Asynchronous memory ready input EMIF − ADDRESS EA21 109 U18 EA20 101 Y18 EA19 100 W17 EA18 95 Y16 EA17 99 V16 EA16 92 Y15 EA15 94 W15 EMIF output clock depends on the EKSRC bit (DEVCFG.[4]) and on EKEN bit (GBLCTL.[5]). EKSRC = 0 – ECLKOUT is based on the internal SYSCLK3 signal from the clock generator (default). EKSRC = 1 – ECLKOUT is based on the the external EMIF input clock source pin (ECLKIN) EKEN = 0 – ECLKOUT held low EKEN = 1 – ECLKOUT enabled to clock (default) Asynchronous memory read enable/SDRAM column-address strobe/SBSRAM address strobe Asynchronous memory output enable/SDRAM row-address strobe/SBSRAM output enable Asynchronous memory write enable/SDRAM write enable/SBSRAM write enable EA14 90 Y14 EMIF external address EA13 91 W14 Note: EMIF address numbering for the C6713BPYP device EA12 93 V14 O/Z IPU starts with EA2 to maintain signal name compatibility with other C671x devices (e.g., C6711, C6713BGDP and C6713BZDP) [see the 32-bit EMIF addressing EA11 86 W13 scheme in the TMS320C6000 DSP External Memory Interface (EMIF) EA10 76 V10 Reference Guide (literature number SPRU266)]. EA9 74 Y9 EA8 71 V9 EA7 70 Y8 EA6 69 W8 EA5 68 V8 EA4 64 W7 EA3 63 V7 EA2 62 Y6 † I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal ‡ IPD = Internal pulldown, IPU = Internal pullup. [To oppose the supply rail on these IPD/IPU signal pins, use external pullup or pulldown resistors no greater than 4.4 kΩ and 2.0 kΩ, respectively.] To maintain signal integrity for the EMIF signals, serial termination resistors should be inserted into all EMIF output signal lines. 52 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
SIGNAL NAME PYP PIN NO. GDP/ ZDP ED31 — N3 ED30 — P3 ED29 — P2 ED28 — P1 ED27 — R2 ED26 — R3 ED25 — T2 ED24 — T1 ED23 — U3 ED22 — U1 ED21 — U2 ED20 — V1 ED19 — V2 ED18 — Y3 ED17 — W4 ED16 — V4 ED15 112 T19 ED14 113 T20 ED13 111 T18 ED12 118 R20 ED11 117 R19 ED10 120 P20 ED9 119 P18 ED8 123 N20 ED7 122 N19 ED6 121 N18 ED5 128 M20 ED4 127 M19 ED3 129 L19 ED2 130 L18 ED1 131 K19 TYPE† Terminal Functions (Continued) IPD/ IPU‡ EMIF − DATA SPRS294A − OCTOBER 2005 − REVISED NOVEMBER 2005 DESCRIPTION I/O/Z IPU External data pins (ED[31:16] pins applicable to GDP and ZDP packages only) ED0 132 K18 † I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal ‡ IPD = Internal pulldown, IPU = Internal pullup. [To oppose the supply rail on these IPD/IPU signal pins, use external pullup or pulldown resistors no greater than 4.4 kΩ and 2.0 kΩ, respectively.] To maintain signal integrity for the EMIF signals, serial termination resistors should be inserted into all EMIF output signal lines. POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 53
Page 1 and 2: SPRS294A − OCTOBER 2005 − REVIS
Page 3 and 4: REVISION HISTORY SPRS294A − OCTOB
Page 5 and 6: GDP and ZDP 272-Ball BGA package (b
Page 13 and 14: functional block and CPU (DSP core)
Page 15 and 16: Á Á Á Á Á Á ÁÁÁÁÁ ÁÁÁ
Page 35 and 36: DEVICE CONFIGURATIONS (CONTINUED) p
Page 37 and 38: DEVICE CONFIGURATIONS (CONTINUED) S
Page 39 and 40: MULTIPLEXED PINS NAME PYP GDP/ ZDP
Page 41 and 42: configuration examples (continued)
Page 47 and 48: DEVICE CONFIGURATIONS (CONTINUED) S
Page 49 and 50: SIGNAL NAME PYP PIN NO. GDP/ ZDP TY
Page 51: SIGNAL NAME PYP PIN NO. GDP/ ZDP HD
Page 55 and 56: SIGNAL NAME PYP PIN NO. GDP/ ZDP TY
Page 57 and 58: SIGNAL NAME PYP PIN NO. GDP/ ZDP SP
Page 59 and 60: SIGNAL NAME PYP PIN NO. GDP/ ZDP 11
Page 61 and 62: VSS SIGNAL NAME PYP PIN NO. GDP/ ZD
Page 63 and 64: VSS SIGNAL NAME PYP PIN NO. GDP/ ZD
Page 75 and 76: EDMA module and EDMA selector (cont
Page 77 and 78: PLL and PLL controller SPRS294A −
Page 85 and 86: multichannel audio serial port (McA
Page 87 and 88: multichannel audio serial port (McA
Page 99 and 100: SPRS294 − OCTOBER 2005 absolute m
Page 101 and 102: PARAMETER MEASUREMENT INFORMATION S
Page 103 and 104:
PARAMETER MEASUREMENT INFORMATION (
Page 105 and 106:
INPUT AND OUTPUT CLOCKS SPRS294 −
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INPUT AND OUTPUT CLOCKS (CONTINUED)
Page 109 and 110:
ASYNCHRONOUS MEMORY TIMING (CONTINU
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SYNCHRONOUS-BURST MEMORY TIMING tim
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SYNCHRONOUS DRAM TIMING timing requ
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SYNCHRONOUS DRAM TIMING (CONTINUED)
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SYNCHRONOUS DRAM TIMING (CONTINUED)
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HOLD/HOLDA TIMING SPRS294 − OCTOB
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timing requirements for reset †
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EXTERNAL INTERRUPT TIMING SPRS294
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MULTICHANNEL AUDIO SERIAL PORT (McA
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INTER-INTEGRATED CIRCUITS (I2C) TIM
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HOST-PORT INTERFACE TIMING SPRS294
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HOST-PORT INTERFACE TIMING (CONTINU
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MULTICHANNEL BUFFERED SERIAL PORT T
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SPRS294 − OCTOBER 2005 switching
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Page 143 and 144:
GENERAL-PURPOSE INPUT/OUTPUT (GPIO)
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MECHANICAL DATA SPRS294 − OCTOBER
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SPRS294 − OCTOBER 2005 packaging
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MECHANICAL DATA MPBG274 - MAY 2002
Page 152:
IMPORTANT NOTICE Texas Instruments
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TMS320C6713B Floating-Point Digital Signal Processor (Rev. A)

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