TMS320C6713B Floating-Point Digital Signal Processor (Rev. A)

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SPRS294A − OCTOBER 2005 − REVISED NOVEMBER 2005 signal groups description (continued) (Transmit/Receive Data Pins) FSR1/AXR0[7] CLKR1/AXR0[6] DX1/AXR0[5] TOUT1/AXR0[4] TINP0/AXR0[3] TOUT0/AXR0[2] DX0/AXR0[1] DR0/AXR0[0] 8-Serial Ports Flexible Partitioning Tx, Rx, OFF (Receive Bit Clock) CLKR0/ACLKR0 CLKS0/AHCLKR0 (Receive Master Clock) Receive Clock Generator Transmit Clock Generator (Transmit Bit Clock) CLKX0/ACLKX0 TINP1/AHCLKX0 (Transmit Master Clock) Receive Clock Check Circuit Transmit Clock Check Circuit FSR0/AFSR0 (Receive Frame Sync or Left/Right Clock) Receive Frame Sync Transmit Frame Sync FSX0/AFSX0 (Transmit Frame Sync or Left/Right Clock) Error Detect (see Note A) Auto Mute Logic CLKX1/AMUTE0 GP[5](EXT_INT5)/AMUTEIN0 McASP0 (Multichannel Audio Serial Port 0) NOTES: A. The McASPs’ Error Detect function detects underruns, overruns, early/late frame syncs, DMA errors, and external mute input. B. On multiplexed pins, bolded text denotes the active function of the pin for that particular peripheral module. C. Bolded and italicized text within parentheses denotes the function of the pins in an audio system. Figure 5. Peripheral <strong>Signal</strong>s (Continued) 30 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
SPRS294A − OCTOBER 2005 − REVISED NOVEMBER 2005 signal groups description (continued) (Transmit/Receive Data Pins) HD1/AXR1[7] HDS1/AXR1[6] HDS2/AXR1[5] HD0/AXR1[4] HCNTL0/AXR1[3] HCS/AXR1[2] HCNTL1/AXR1[1] HR/W/AXR1[0] 8-Serial Ports Flexible Partitioning Tx, Rx, OFF (Receive Bit Clock) HRDY/ACLKR1 HD6/AHCLKR1 (Receive Master Clock) Receive Clock Generator Transmit Clock Generator (Transmit Bit Clock) HAS/ACLKX1 HD5/AHCLKX1 (Transmit Master Clock) Receive Clock Check Circuit Transmit Clock Check Circuit HHWIL/AFSR1 (Receive Frame Sync or Left/Right Clock) Receive Frame Sync Transmit Frame Sync HD2/AFSX1 (Transmit Frame Sync or Left/Right Clock) Error Detect (see Note A) Auto Mute Logic HD3/AMUTE1 GP[4](EXT_INT4)/AMUTEIN1 McASP1 (Multichannel Audio Serial Port 1) NOTES: A. The McASPs’ Error Detect function detects underruns, overruns, early/late frame syncs, DMA errors, and external mute input. B. On multiplexed pins, bolded text denotes the active function of the pin for that particular peripheral module. C. Bolded and italicized text within parentheses denotes the function of the pins in an audio system. Figure 5. Peripheral <strong>Signal</strong>s (Continued) POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 31
Page 1 and 2: SPRS294A − OCTOBER 2005 − REVIS
Page 3 and 4: REVISION HISTORY SPRS294A − OCTOB
Page 5 and 6: GDP and ZDP 272-Ball BGA package (b
Page 13 and 14: functional block and CPU (DSP core)
Page 15 and 16: Á Á Á Á Á Á ÁÁÁÁÁ ÁÁÁ
Page 29: SPRS294A − OCTOBER 2005 − REVIS
Page 35 and 36: DEVICE CONFIGURATIONS (CONTINUED) p
Page 37 and 38: DEVICE CONFIGURATIONS (CONTINUED) S
Page 39 and 40: MULTIPLEXED PINS NAME PYP GDP/ ZDP
Page 41 and 42: configuration examples (continued)
Page 47 and 48: DEVICE CONFIGURATIONS (CONTINUED) S
Page 49 and 50: SIGNAL NAME PYP PIN NO. GDP/ ZDP TY
Page 51 and 52: SIGNAL NAME PYP PIN NO. GDP/ ZDP HD
Page 53 and 54: SIGNAL NAME PYP PIN NO. GDP/ ZDP ED
Page 55 and 56: SIGNAL NAME PYP PIN NO. GDP/ ZDP TY
Page 57 and 58: SIGNAL NAME PYP PIN NO. GDP/ ZDP SP
Page 59 and 60: SIGNAL NAME PYP PIN NO. GDP/ ZDP 11
Page 61 and 62: VSS SIGNAL NAME PYP PIN NO. GDP/ ZD
Page 63 and 64: VSS SIGNAL NAME PYP PIN NO. GDP/ ZD
Page 75 and 76: EDMA module and EDMA selector (cont
Page 77 and 78: PLL and PLL controller SPRS294A −
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SPRS294A − OCTOBER 2005 − REVIS
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multichannel audio serial port (McA
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multichannel audio serial port (McA
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SPRS294 − OCTOBER 2005 absolute m
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PARAMETER MEASUREMENT INFORMATION S
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PARAMETER MEASUREMENT INFORMATION (
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INPUT AND OUTPUT CLOCKS SPRS294 −
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INPUT AND OUTPUT CLOCKS (CONTINUED)
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ASYNCHRONOUS MEMORY TIMING (CONTINU
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SYNCHRONOUS-BURST MEMORY TIMING tim
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SYNCHRONOUS DRAM TIMING timing requ
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SYNCHRONOUS DRAM TIMING (CONTINUED)
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SYNCHRONOUS DRAM TIMING (CONTINUED)
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HOLD/HOLDA TIMING SPRS294 − OCTOB
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timing requirements for reset †
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EXTERNAL INTERRUPT TIMING SPRS294
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MULTICHANNEL AUDIO SERIAL PORT (McA
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INTER-INTEGRATED CIRCUITS (I2C) TIM
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HOST-PORT INTERFACE TIMING SPRS294
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HOST-PORT INTERFACE TIMING (CONTINU
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MULTICHANNEL BUFFERED SERIAL PORT T
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SPRS294 − OCTOBER 2005 switching
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GENERAL-PURPOSE INPUT/OUTPUT (GPIO)
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MECHANICAL DATA SPRS294 − OCTOBER
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SPRS294 − OCTOBER 2005 packaging
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MECHANICAL DATA MPBG274 - MAY 2002
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IMPORTANT NOTICE Texas Instruments
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TMS320C6713B Floating-Point Digital Signal Processor (Rev. A)

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