TMS320C6713B Floating-Point Digital Signal Processor (Rev. A)
TMS320C6713B Floating-Point Digital Signal Processor (Rev. A)
TMS320C6713B Floating-Point Digital Signal Processor (Rev. A)
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SPRS294A − OCTOBER 2005 − REVISED NOVEMBER 2005<br />
configuration examples (continued)<br />
DEVICE CONFIGURATIONS (CONTINUED)<br />
ED [31:16],<br />
ED[15:0]<br />
EA[21:2]<br />
CE[3:0], BE[3:0],<br />
HOLDA, HOLD,<br />
BUSREQ, ECLKIN,<br />
ECLKOUT,<br />
ARE/SDCAS/SSADS,<br />
AWE/SDWE/SSWE,<br />
AOE/SDRAS/SSOE,<br />
ARDY<br />
32<br />
20<br />
EMIF<br />
Clock,<br />
System,<br />
EMU, and<br />
Reset<br />
GPIO<br />
and<br />
EXT_INT<br />
CLKIN, CLKOUT3, CLKMODE0,<br />
PLLHV, TMS, TDO, TDI, TCK,<br />
TRST, EMU[5:3,1,0], RESET,<br />
NMI<br />
GP[15:8, 3:1]<br />
GP[0],<br />
GP[4](EXT_INT4)/AMUTEIN1,<br />
GP[5](EXT_INT5)/AMUTEIN0,<br />
GP[6](EXT_INT6),<br />
GP[7](EXT_INT7)<br />
HPI<br />
I2C0<br />
SCL0, SDA0<br />
I2C1<br />
McASP1<br />
8<br />
AFSX1, AFSR1, ACLKX1,<br />
ACLKR1, AHCLKR1,<br />
AHCLKX1, AMUTE1<br />
AXR1[7:0]<br />
DR1, CLKS1,<br />
CLKR1, CLKX1,<br />
FSR1, DX1,<br />
FSX1<br />
McBSP1<br />
McASP0<br />
TIMER0<br />
5<br />
AXR0[4:0]<br />
{TINP0/AXR0[3]}<br />
TINP1/AHCLKX0,<br />
AHCLKR0,<br />
ACLKR0,<br />
ACLKX0, AFSR0,<br />
AFSX0<br />
McBSP0<br />
TIMER1<br />
Shading denotes a peripheral module not available for this configuration.<br />
DEVCFG Register Value:<br />
0x0000 000E<br />
MCBSP0DIS = 1<br />
MCBSP1DIS = 0<br />
TOUT0SEL = 1<br />
TOUT1SEL = 1<br />
EKSRC = 0<br />
HPI_EN(HD14) = 0<br />
GP2EN BIT = 1 (enabling GPEN.[2])<br />
Figure 7. Configuration Example B (1 I2C + 1 McBSP + 2 McASP + GPIO)<br />
42 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
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