TMS320C6713B Floating-Point Digital Signal Processor (Rev. A)
TMS320C6713B Floating-Point Digital Signal Processor (Rev. A)
TMS320C6713B Floating-Point Digital Signal Processor (Rev. A)
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SPRS294 − OCTOBER 2005<br />
JTAG TEST-PORT TIMING<br />
timing requirements for JTAG test port (see Figure 67)<br />
NO.<br />
PYP-200,-225<br />
GDP/ZDP -225, -300<br />
PYPA<br />
-167, -200 UNIT<br />
GDPA/ZDPA −200<br />
MIN MAX<br />
1 tc(TCK) Cycle time, TCK 35 ns<br />
3 tsu(TDIV-TCKH) Setup time, TDI/TMS/TRST valid before TCK high 10 ns<br />
4 th(TCKH-TDIV) Hold time, TDI/TMS/TRST valid after TCK high 7 ns<br />
switching characteristics over recommended operating conditions for JTAG test port<br />
(see Figure 67)<br />
NO.<br />
PARAMETER<br />
PYP-200,-225<br />
GDP/ZDP -225, -300<br />
PYPA<br />
-167, -200<br />
GDPA/ZDPA −200<br />
UNIT<br />
MIN MAX<br />
2 td(TCKL-TDOV) Delay time, TCK low to TDO valid 0 15 ns<br />
TCK<br />
1<br />
2<br />
2<br />
TDO<br />
3<br />
4<br />
TDI/TMS/TRST<br />
Figure 67. JTAG Test-Port Timing<br />
144 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
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