TMS320C6713B Floating-Point Digital Signal Processor (Rev. A)

timing requirements for reset †‡ (see Figure 49)
RESET TIMING
SPRS294 − OCTOBER 2005
NO.
PYP-200,-225
GDP/ZDP -225, -300
PYPA -167, -200 UNIT
GDPA/ZDPA −200
MIN MAX
1 tw(RST) Pulse duration, RESET 100 ns
13 tsu(HD) Setup time, HD boot configuration bits valid before RESET high§ 2P ns
14 th(HD) Hold time, HD boot configuration bits valid after RESET high§ 2P ns
† P = 1/CPU clock frequency in ns. For example, when running parts at 300 MHz, use P = 3.3 ns.
‡ For the C6713B device, the PLL is bypassed immediately after the device comes out of reset. The PLL Controller can be programmed to change
the PLL mode in software. For more detailed information on the PLL Controller, see the TMS320C6000 DSP Phase-Lock Loop (PLL) Controller
Peripheral Reference Guide (literature number SPRU233).
§ The Boot and device configurations bits are latched asynchronously when RESET is transitioning high. The Boot and device configurations bits
consist of: HD[14, 8, 4:3].
switching characteristics over recommended operating conditions during reset (see Figure 49)
NO.
2 td(RSTH-ZV)
PARAMETER
Delay time, external RESET high to internal reset high and
all signal groups valid#|| CLKMODE0 = 1
PYP-200,-225
GDP/ZDP -225, -300
PYPA-167, -200
GDPA/ZDPA −200
MIN MAX
512 x CLKIN
period
3 td(RSTL-ECKOL) Delay time, RESET low to ECLKOUT high impedance 0 ns
4 td(RSTH-ECKOV) Delay time, RESET high to ECLKOUT valid 6P ns
5 td(RSTL-CKO2IV) Delay time, RESET low to CLKOUT2 high impedance 0 ns
6 td(RSTH-CKO2V) Delay time, RESET high to CLKOUT2 valid 6P ns
7 td(RSTL-CKO3L) Delay time, RESET low to CLKOUT3 low 0 ns
8 td(RSTH-CKO3V) Delay time, RESET high to CLKOUT3 valid 6P ns
9 td(RSTL-EMIFZHZ) Delay time, RESET low to EMIF Z group high impedance|| 0 ns
10 td(RSTL-EMIFLIV) Delay time, RESET low to EMIF low group (BUSREQ) invalid|| 0 ns
11 td(RSTL-Z1HZ) Delay time, RESET low to Z group 1 high impedance|| 0 ns
12 td(RSTL-Z2HZ) Delay time, RESET low to Z group 2 high impedance|| 0 ns
P = 1/CPU clock frequency in ns.
Note that while internal reset is asserted low, the CPU clock (SYSCLK1) period is equal to the input clock (CLKIN) period multiplied by 8. For
example, if the CLKIN period is 20 ns, then the CPU clock (SYSCLK1) period is 20 ns x 8 = 160 ns. Therefore, P = SYSCLK1 = 160 ns while
internal reset is asserted.
# The internal reset is stretched exactly 512 x CLKIN cycles if CLKIN is used (CLKMODE0 = 1). If the input clock (CLKIN) is not stable when RESET
is deasserted, the actual delay time may vary.
|| EMIF Z group consists of: EA[21:2], ED[31:0], CE[3:0], BE[3:0], ARE/SDCAS/SSADS, AWE/SDWE/SSWE, AOE/SDRAS/SSOE and
HOLDA
EMIF low group consists of: BUSREQ
Z group 1 consists of: CLKR0/ACLKR0, CLKR1/AXR0[6], CLKX0/ACLKX0, CLKX1/AMUTE0, FSR0/AFSR0, FSR1/AXR0[7],
FSX0/AFSX0, FSX1, DX0/AXR0[1], DX1/AXR0[5], TOUT0/AXR0[2], TOUT1/AXR0[4], SDA0 and SCL0.
Z group 2 consists of: All other HPI, McASP0/1, GPIO, and I2C1 signals.
UNIT
ns
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