TMS320C6713B Floating-Point Digital Signal Processor (Rev. A)

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SPRS294 − OCTOBER 2005 RESET TIMING (CONTINUED) Phase 1 Phase 2 Phase 3 CLKIN ECLKIN RESET Internal Reset Internal SYSCLK1 Internal SYSCLK2 Internal SYSCLK3 ECLKOUT CLKOUT2 CLKOUT3 EMIF Z Group† EMIF Low Group† Z Group 1† Z Group 2† 3 5 7 9 10 11 12 1 4 6 8 14 Boot and Device 13 Configuration Pins‡ † EMIF Z group consists of: EA[21:2], ED[31:0], CE[3:0], BE[3:0], ARE/SDCAS/SSADS, AWE/SDWE/SSWE, AOE/SDRAS/SSOE and HOLDA EMIF low group consists of: BUSREQ Z group 1 consists of: CLKR0/ACLKR0, CLKR1/AXR0[6], CLKX0/ACLKX0, CLKX1/AMUTE0, FSR0/AFSR0, FSR1/AXR0[7], FSX0/AFSX0, FSX1, DX0/AXR0[1], DX1/AXR0[5], TOUT0/AXR0[2], TOUT1/AXR0[4], SDA0 and SCL0. Z group 2 consists of: All other HPI, McASP0/1, GPIO, and I2C1 signals. ‡ Boot and device configurations consist of: HD[14, 8, 4:3]. Figure 49. Reset Timing Reset Phase 1: The RESET pin is asserted. During this time, all internal clocks are running at the CLKIN frequency divide-by-8. The CPU is also running at the CLKIN frequency divide-by-8. Reset Phase 2: The RESET pin is deasserted but the internal reset is stretched. During this time, all internal clocks are running at the CLKIN frequency divide-by-8. The CPU is also running at the CLKIN frequency divide-by-8. Reset Phase 3: Both the RESET pin and internal reset are deasserted. During this time, all internal clocks are running at their default divide-down frequency of CLKIN. The CPU clock (SYSCLK1) is running at CLKIN frequency. The peripheral clock (SYSCLK2) is running at CLKIN frequency divide-by-2. The EMIF internal clock source (SYSCLK3) is running at CLKIN frequency divide-by-2. SYSCLK3 is reflected on the ECLKOUT pin (when EKSRC bit = 0 [default]). CLKOUT3 is running at CLKIN frequency divide-by-8. 2 2 2 2 2 122 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
EXTERNAL INTERRUPT TIMING SPRS294 − OCTOBER 2005 timing requirements for external interrupts † (see Figure 50) NO. PYP-200,-225 GDP/ZDP -225, -300 PYPA -167, -200 GDPA/ZDPA −200 UNIT MIN MAX 1 tw(ILOW) Width of the NMI interrupt pulse low 2P ns Width of the EXT_INT interrupt pulse low 4P ns 2 tw(IHIGH) Width of the NMI interrupt pulse high 2P ns Width of the EXT_INT interrupt pulse high 4P ns † P = 1/CPU clock frequency in ns. For example, when running parts at 300 MHz, use P = 3.3 ns. EXT_INT, NMI 1 2 Figure 50. External/NMI Interrupt Timing POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 123
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SPRS294A − OCTOBER 2005 − REVIS
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REVISION HISTORY SPRS294A − OCTOB
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GDP and ZDP 272-Ball BGA package (b
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functional block and CPU (DSP core)
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DEVICE CONFIGURATIONS (CONTINUED) p
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DEVICE CONFIGURATIONS (CONTINUED) S
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MULTIPLEXED PINS NAME PYP GDP/ ZDP
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configuration examples (continued)
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DEVICE CONFIGURATIONS (CONTINUED) S
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SIGNAL NAME PYP PIN NO. GDP/ ZDP TY
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SIGNAL NAME PYP PIN NO. GDP/ ZDP HD
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SIGNAL NAME PYP PIN NO. GDP/ ZDP ED
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SIGNAL NAME PYP PIN NO. GDP/ ZDP TY
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SIGNAL NAME PYP PIN NO. GDP/ ZDP SP
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SIGNAL NAME PYP PIN NO. GDP/ ZDP 11
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VSS SIGNAL NAME PYP PIN NO. GDP/ ZD
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VSS SIGNAL NAME PYP PIN NO. GDP/ ZD
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Page 71 and 72: SPRS294A − OCTOBER 2005 − REVIS
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Page 87 and 88: multichannel audio serial port (McA
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Page 107 and 108: INPUT AND OUTPUT CLOCKS (CONTINUED)
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Page 121: timing requirements for reset †
Page 125 and 126: MULTICHANNEL AUDIO SERIAL PORT (McA
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Page 139 and 140: SPRS294 − OCTOBER 2005 switching
Page 143 and 144: GENERAL-PURPOSE INPUT/OUTPUT (GPIO)
Page 145 and 146: MECHANICAL DATA SPRS294 − OCTOBER
Page 147 and 148: SPRS294 − OCTOBER 2005 packaging
Page 149 and 150: MECHANICAL DATA MPBG274 - MAY 2002
Page 152: IMPORTANT NOTICE Texas Instruments
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TMS320C6713B Floating-Point Digital Signal Processor (Rev. A)

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