TMS320C6713B Floating-Point Digital Signal Processor (Rev. A)
TMS320C6713B Floating-Point Digital Signal Processor (Rev. A)
TMS320C6713B Floating-Point Digital Signal Processor (Rev. A)
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MULTICHANNEL BUFFERED SERIAL PORT TIMING (CONTINUED)<br />
SPRS294 − OCTOBER 2005<br />
timing requirements for FSR when GSYNC = 1 (see Figure 60)<br />
NO.<br />
PYP-200,-225<br />
GDP/ZDP -225, -300<br />
PYPA -167, -200<br />
GDPA/ZDPA −200<br />
UNIT<br />
MIN MAX<br />
1 tsu(FRH-CKSH) Setup time, FSR high before CLKS high 4 ns<br />
2 th(CKSH-FRH) Hold time, FSR high after CLKS high 4 ns<br />
CLKS<br />
FSR external<br />
CLKR/X (no need to resync)<br />
CLKR/X (needs resync)<br />
1<br />
2<br />
Figure 60. FSR Timing When GSYNC = 1<br />
timing requirements for McBSP as SPI master or slave: CLKSTP = 10b, CLKXP = 0 †‡ (see Figure 61)<br />
NO.<br />
PYP-200,-225<br />
GDP/ZDP -225, -300<br />
PYPA -167, -200<br />
GDPA/ZDPA −200<br />
UNIT<br />
MASTER<br />
SLAVE<br />
MIN MAX MIN MAX<br />
4 tsu(DRV-CKXL) Setup time, DR valid before CLKX low 12 2 − 6P ns<br />
5 th(CKXL-DRV) Hold time, DR valid after CLKX low 4 5 + 12P ns<br />
† P = 1/CPU clock frequency in ns. For example, when running parts at 300 MHz, use P = 3.3 ns.<br />
‡ For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1.<br />
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443<br />
135
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