TMS320C6713B Floating-Point Digital Signal Processor (Rev. A)

SIGNAL
NAME
PYP
PIN NO.
GDP/
ZDP
TYPE†
Terminal Functions (Continued)
IPD/
IPU‡
SPRS294A − OCTOBER 2005 − REVISED NOVEMBER 2005
DESCRIPTION
MULTICHANNEL AUDIO SERIAL PORT 0 (McASP0) (CONTINUED)
CLKR1/AXR0[6] 36 M1 I/O/Z IPD McBSP1 receive clock (I/O/Z) [default] or McASP0 TX/RX data pin 6 (I/O/Z).
DX1/AXR0[5] 32 L2 I/O/Z IPU McBSP1 transmit data (O/Z) [default] or McASP0 TX/RX data pin 5 (I/O/Z).
TOUT1/AXR0[4] 13 F1 I/O/Z IPD Timer 1 output (O) [default] or McASP0 TX/RX data pin 4 (I/O/Z).
TINP0/AXR0[3] 17 G2 I/O/Z IPD Timer 0 input (I) [default] or McASP0 TX/RX data pin 3 (I/O/Z).
TOUT0/AXR0[2] 18 G1 I/O/Z IPD Timer 0 output (O) [default] or McASP0 TX/RX data pin 2 (I/O/Z).
DX0/AXR0[1] 20 H2 I/O/Z IPU McBSP0 transmit data (O/Z) [default] or McASP0 TX/RX data pin 1 (I/O/Z).
DR0/AXR0[0] 27 J1 I/O/Z IPU McBSP0 receive data (I) [default] or McASP0 TX/RX data pin 0 (I/O/Z).
TIMER 1
TOUT1/AXR0[4] 13 F1 O IPD Timer 1 output (O) [default] or McASP0 TX/RX data pin 4 (I/O/Z).
TINP1/AHCLKX0 12 F2 I IPD
Timer 1 input (I) or McASP0 transmit high−frequency master clock (I/O/Z). This
pin defaults as Timer 1 input (I) and McASP transmit high−frequency master
clock input (I).
TIMER0
TOUT0/AXR0[2] 18 G1 O IPD Timer 0 output (O) [default] or McASP0 TX/RX data pin 2 (I/O/Z).
TINP0/AXR0[3] 17 G2 I IPD Timer 0 input (I) [default] or McASP0 TX/RX data pin 3 (I/O/Z).
CLKS1/SCL1 8 E1 I —
MULTICHANNEL BUFFERED SERIAL PORT 1 (McBSP1)
McBSP1 external clock source (as opposed to internal) (I) [default] or I2C1
clock (I/O/Z).
This pin does not have an internal pullup or pulldown. When this pin is used as a
McBSP pin, this pin should either be driven externally at all times or be pulled up
with a 10-kΩ resistor to a valid logic level. Because it is common for some ICs to
3-state their outputs at times, a 10-kΩ pullup resistor may be desirable even
when an external device is driving the pin.
CLKR1/AXR0[6] 36 M1 I/O/Z IPD McBSP1 receive clock (I/O/Z) [default] or McASP0 TX/RX data pin 6 (I/O/Z).
CLKX1/AMUTE0 33 L3 I/O/Z IPD McBSP1 transmit clock (I/O/Z) [default] or McASP0 mute output (O/Z).
DR1/SDA1 37 M2 I —
McBSP1 receive data (I) [default] or I2C1 data (I/O/Z).
This pin does not have an internal pullup or pulldown. When this pin is used as a
McBSP pin, this pin should either be driven externally at all times or be pulled up
with a 10-kΩ resistor to a valid logic level. Because it is common for some ICs to
3-state their outputs at times, a 10-kΩ pullup resistor may be desirable even
when an external device is driving the pin.
DX1/AXR0[5] 32 L2 O/Z IPU McBSP1 transmit data (O/Z) [default] or McASP0 TX/RX data pin 5 (I/O/Z).
FSR1/AXR0[7] 38 M3 I/O/Z IPD
McBSP1 receive frame sync (I/O/Z) [default] or McASP0 TX/RX data pin 7
(I/O/Z).
FSX1 31 L1 I/O/Z IPD McBSP1 transmit frame sync
† I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal
‡ IPD = Internal pulldown, IPU = Internal pullup. [To oppose the supply rail on these IPD/IPU signal pins, use external pullup or pulldown resistors
no greater than 4.4 kΩ and 2.0 kΩ, respectively.]
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
55