TMS320C6713B Floating-Point Digital Signal Processor (Rev. A)

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SPRS294A − OCTOBER 2005 − REVISED NOVEMBER 2005 PLL and PLL controller (continued) Table 36. PLL Control/Status Register (PLLCSR) [0x01B7 C100] 31 28 27 24 23 20 19 16 Reserved R−0 15 12 11 8 7 6 5 4 3 2 1 0 Reserved STABLE Reserved PLLRST Reserved PLLPWRDN PLLEN R−0 R−x R−0 RW−1 R/W−0 R/W−0b RW−0 Legend: R = Read only, R/W = Read/Write; -n = value after reset Table 37. PLL Control/Status Register (PLLCSR) Description BIT # NAME DESCRIPTION 31:7 Reserved Reserved. Read-only, writes have no effect. Clock Input Stable. This bit indicates if the clock input has stabilized. 6 STABLE 0 – Clock input not yet stable. Clock counter is not finished counting (default). 1 – Clock input stable. 5:4 Reserved Reserved. Read-only, writes have no effect. Asserts RESET to PLL 3 PLLRST 0 – PLL Reset Released. 1 – PLL Reset Asserted (default). 2 Reserved Reserved. The user must write a “0” to this bit. 1 PLLPWRDN 0 PLLEN Select PLL Power Down 0 – PLL Operational (default). 1 – PLL Placed in Power-Down State. PLL Mode Enable 0 – Bypass Mode (default). PLL disabled. Divider D0 and PLL are bypassed. SYSCLK1/SYSCLK2/SYSCLK3 are divided down directly from input reference clock. 1 – PLL Enabled. Divider D0 and PLL are not bypassed. SYSCLK1/SYSCLK2/SYSCLK3 are divided down from PLL output. 80 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
SPRS294A − OCTOBER 2005 − REVISED NOVEMBER 2005 PLL and PLL controller (continued) Table 38. PLL Multiplier Control Register (PLLM) [0x01B7 C110] 31 28 27 24 23 20 19 16 Reserved R−0 15 12 11 8 7 6 5 4 3 2 1 0 Reserved PLLM R−0 R/W−0 0111 Legend: R = Read only, R/W = Read/Write; -n = value after reset Table 39. PLL Multiplier Control Register (PLLM) Description BIT # NAME DESCRIPTION 31:5 Reserved Reserved. Read-only, writes have no effect. 4:0 PLLM PLL multiply mode [default is x7 (0 0111)]. 00000 = Reserved 10000 = x16 00001 = Reserved 10001 = x17 00010 = Reserved 10010 = x18 00011 = Reserved 10011 = x19 00100 = x4 10100 = x20 00101 = x5 10101 = x21 00110 = x6 10110 = x22 00111 = x7 10111 = x23 01000 = x8 11000 = x24 01001 = x9 11001 = x25 01010 = x10 11010 = Reserved 01011 = x11 11011 = Reserved 01100 = x12 11100 = Reserved 01101 = x13 11101 = Reserved 01110 = x14 11110 = Reserved 01111 = x15 11111 = Reserved PLLM select values 00000 through 00011 and 11010 through 11111 are not supported. POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 81
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SPRS294A − OCTOBER 2005 − REVIS
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REVISION HISTORY SPRS294A − OCTOB
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GDP and ZDP 272-Ball BGA package (b
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functional block and CPU (DSP core)
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Page 35 and 36: DEVICE CONFIGURATIONS (CONTINUED) p
Page 37 and 38: DEVICE CONFIGURATIONS (CONTINUED) S
Page 39 and 40: MULTIPLEXED PINS NAME PYP GDP/ ZDP
Page 41 and 42: configuration examples (continued)
Page 47 and 48: DEVICE CONFIGURATIONS (CONTINUED) S
Page 49 and 50: SIGNAL NAME PYP PIN NO. GDP/ ZDP TY
Page 51 and 52: SIGNAL NAME PYP PIN NO. GDP/ ZDP HD
Page 53 and 54: SIGNAL NAME PYP PIN NO. GDP/ ZDP ED
Page 55 and 56: SIGNAL NAME PYP PIN NO. GDP/ ZDP TY
Page 57 and 58: SIGNAL NAME PYP PIN NO. GDP/ ZDP SP
Page 59 and 60: SIGNAL NAME PYP PIN NO. GDP/ ZDP 11
Page 61 and 62: VSS SIGNAL NAME PYP PIN NO. GDP/ ZD
Page 63 and 64: VSS SIGNAL NAME PYP PIN NO. GDP/ ZD
Page 75 and 76: EDMA module and EDMA selector (cont
Page 77 and 78: PLL and PLL controller SPRS294A −
Page 79: SPRS294A − OCTOBER 2005 − REVIS
Page 85 and 86: multichannel audio serial port (McA
Page 87 and 88: multichannel audio serial port (McA
Page 99 and 100: SPRS294 − OCTOBER 2005 absolute m
Page 101 and 102: PARAMETER MEASUREMENT INFORMATION S
Page 103 and 104: PARAMETER MEASUREMENT INFORMATION (
Page 105 and 106: INPUT AND OUTPUT CLOCKS SPRS294 −
Page 107 and 108: INPUT AND OUTPUT CLOCKS (CONTINUED)
Page 109 and 110: ASYNCHRONOUS MEMORY TIMING (CONTINU
Page 111 and 112: SYNCHRONOUS-BURST MEMORY TIMING tim
Page 113 and 114: SYNCHRONOUS DRAM TIMING timing requ
Page 115 and 116: SYNCHRONOUS DRAM TIMING (CONTINUED)
Page 117 and 118: SYNCHRONOUS DRAM TIMING (CONTINUED)
Page 119 and 120: HOLD/HOLDA TIMING SPRS294 − OCTOB
Page 121 and 122: timing requirements for reset †
Page 123 and 124: EXTERNAL INTERRUPT TIMING SPRS294
Page 125 and 126: MULTICHANNEL AUDIO SERIAL PORT (McA
Page 127 and 128: INTER-INTEGRATED CIRCUITS (I2C) TIM
Page 129 and 130: HOST-PORT INTERFACE TIMING SPRS294
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HOST-PORT INTERFACE TIMING (CONTINU
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MULTICHANNEL BUFFERED SERIAL PORT T
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SPRS294 − OCTOBER 2005 switching
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GENERAL-PURPOSE INPUT/OUTPUT (GPIO)
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MECHANICAL DATA SPRS294 − OCTOBER
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SPRS294 − OCTOBER 2005 packaging
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MECHANICAL DATA MPBG274 - MAY 2002
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IMPORTANT NOTICE Texas Instruments
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TMS320C6713B Floating-Point Digital Signal Processor (Rev. A)

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