TMS320C6713B Floating-Point Digital Signal Processor (Rev. A)
TMS320C6713B Floating-Point Digital Signal Processor (Rev. A)
TMS320C6713B Floating-Point Digital Signal Processor (Rev. A)
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PLL and PLL controller<br />
SPRS294A − OCTOBER 2005 − REVISED NOVEMBER 2005<br />
The <strong>TMS320C6713B</strong> includes a PLL and a flexible PLL Controller peripheral consisting of a prescaler (D0) and<br />
four dividers (OSCDIV1, D1, D2, and D3). The PLL controller is able to generate different clocks for different<br />
parts of the system (i.e., DSP core, Peripheral Data Bus, External Memory Interface, McASP, and other<br />
peripherals). Figure 15 illustrates the PLL, the PLL controller, and the clock generator logic.<br />
+3.3 V<br />
EMI filter<br />
C1<br />
C2<br />
10 µF 0.1 µF<br />
PLLHV<br />
CLKMODE0<br />
CLKIN<br />
PLLREF<br />
PLLOUT<br />
For Use<br />
in System<br />
Reserved<br />
CLKOUT3<br />
ECLKIN<br />
1<br />
0<br />
OSCDIV1<br />
/1, /2,<br />
..., /32<br />
ENA<br />
OD1EN (OSCDIV1.[15])<br />
DIVIDER D0<br />
/1, /2,<br />
..., /32<br />
ENA<br />
PLL<br />
x4 to x25<br />
1<br />
0<br />
D1EN (PLLDIV1.[15])<br />
D0EN (PLLDIV0.[15])<br />
D2EN (PLLDIV2.[15])<br />
AUXCLK<br />
(Internal Clock Source<br />
to McASP0 and McASP1)<br />
D3EN (PLLDIV3.[15])<br />
PLLEN (PLL_CSR.[0])<br />
DIVIDER D1 †<br />
/1, /2,<br />
..., /32<br />
ENA<br />
DIVIDER D2 †<br />
/1, /2,<br />
..., /32<br />
ENA<br />
DIVIDER D3<br />
/1, /2,<br />
..., /32<br />
ENA<br />
SYSCLK1<br />
(DSP Core)<br />
SYSCLK2<br />
(Peripherals)<br />
SYSCLK3<br />
(EMIF Clock Input)<br />
C6713B DSP<br />
1 0<br />
EMIF<br />
EKSRC Bit<br />
(DEVCFG.[4])<br />
ECLKOUT<br />
† Dividers D1 and D2 must never be disabled. Never write a “0” to the D1EN or D2EN bits in the PLLDIV1 and PLLDIV2 registers.<br />
NOTES: A. Place all PLL external components (C1, C2, and the EMI Filter) as close to the C67x DSP device as possible. For the best<br />
performance, TI recommends that all the PLL external components be on a single side of the board without jumpers, switches, or<br />
components other than the ones shown.<br />
B. For reduced PLL jitter, maximize the spacing between switching signals and the PLL external components (C1, C2, and the EMI<br />
Filter).<br />
C. The 3.3-V supply for the EMI filter must be from the same 3.3-V power plane supplying the I/O voltage, DVDD.<br />
D. EMI filter manufacturer TDK part number ACF451832-333, -223, -153, -103. Panasonic part number EXCCET103U.<br />
Figure 15. PLL and Clock Generator Logic<br />
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443<br />
77
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