TMS320C6713B Floating-Point Digital Signal Processor (Rev. A)

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SPRS294A − OCTOBER 2005 − REVISED NOVEMBER 2005 VSS SIGNAL NAME PYP PIN NO. GDP/ ZDP — N4 — N17 — P4 — P17 — P19 — T4 — T17 — U4 — U8 — U9 — U13 — U17 — U20 — W1 — W5 — W11 — W16 — W20 — Y1 — Y2 — Y13 — Y19 — Y20 4 — 10 — 15 — 23 — 26 — 30 — 34 — 39 — 45 — 48 — 49 — 52 — 54 — 59 — 66 — 73 — TYPE† GND Terminal Functions (Continued) Ground pins GROUND PINS (CONTINUED) DESCRIPTION 81 — † I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal 62 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
VSS SIGNAL NAME PYP PIN NO. GDP/ ZDP 85 — 88 — 97 — 106 — 115 — 125 — 134 — 142 — 148 — 158 — 163 — 170 — 182 — 189 — 194 — 199 — 203 — TYPE† GND Terminal Functions (Continued) Ground pins GROUND PINS (CONTINUED) SPRS294A − OCTOBER 2005 − REVISED NOVEMBER 2005 DESCRIPTION 207 — † I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 63
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SPRS294A − OCTOBER 2005 − REVIS
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REVISION HISTORY SPRS294A − OCTOB
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GDP and ZDP 272-Ball BGA package (b
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Page 9 and 10:
Page 11 and 12: SPRS294A − OCTOBER 2005 − REVIS
Page 13 and 14: functional block and CPU (DSP core)
Page 15 and 16: Á Á Á Á Á Á ÁÁÁÁÁ ÁÁÁ
Page 35 and 36: DEVICE CONFIGURATIONS (CONTINUED) p
Page 37 and 38: DEVICE CONFIGURATIONS (CONTINUED) S
Page 39 and 40: MULTIPLEXED PINS NAME PYP GDP/ ZDP
Page 41 and 42: configuration examples (continued)
Page 47 and 48: DEVICE CONFIGURATIONS (CONTINUED) S
Page 49 and 50: SIGNAL NAME PYP PIN NO. GDP/ ZDP TY
Page 51 and 52: SIGNAL NAME PYP PIN NO. GDP/ ZDP HD
Page 53 and 54: SIGNAL NAME PYP PIN NO. GDP/ ZDP ED
Page 55 and 56: SIGNAL NAME PYP PIN NO. GDP/ ZDP TY
Page 57 and 58: SIGNAL NAME PYP PIN NO. GDP/ ZDP SP
Page 59 and 60: SIGNAL NAME PYP PIN NO. GDP/ ZDP 11
Page 61: VSS SIGNAL NAME PYP PIN NO. GDP/ ZD
Page 75 and 76: EDMA module and EDMA selector (cont
Page 77 and 78: PLL and PLL controller SPRS294A −
Page 85 and 86: multichannel audio serial port (McA
Page 87 and 88: multichannel audio serial port (McA
Page 99 and 100: SPRS294 − OCTOBER 2005 absolute m
Page 101 and 102: PARAMETER MEASUREMENT INFORMATION S
Page 103 and 104: PARAMETER MEASUREMENT INFORMATION (
Page 105 and 106: INPUT AND OUTPUT CLOCKS SPRS294 −
Page 107 and 108: INPUT AND OUTPUT CLOCKS (CONTINUED)
Page 109 and 110: ASYNCHRONOUS MEMORY TIMING (CONTINU
Page 111 and 112: SYNCHRONOUS-BURST MEMORY TIMING tim
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SYNCHRONOUS DRAM TIMING timing requ
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SYNCHRONOUS DRAM TIMING (CONTINUED)
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SYNCHRONOUS DRAM TIMING (CONTINUED)
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HOLD/HOLDA TIMING SPRS294 − OCTOB
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timing requirements for reset †
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EXTERNAL INTERRUPT TIMING SPRS294
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MULTICHANNEL AUDIO SERIAL PORT (McA
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INTER-INTEGRATED CIRCUITS (I2C) TIM
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HOST-PORT INTERFACE TIMING SPRS294
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HOST-PORT INTERFACE TIMING (CONTINU
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MULTICHANNEL BUFFERED SERIAL PORT T
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Page 139 and 140:
SPRS294 − OCTOBER 2005 switching
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Page 143 and 144:
GENERAL-PURPOSE INPUT/OUTPUT (GPIO)
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MECHANICAL DATA SPRS294 − OCTOBER
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SPRS294 − OCTOBER 2005 packaging
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MECHANICAL DATA MPBG274 - MAY 2002
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IMPORTANT NOTICE Texas Instruments
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TMS320C6713B Floating-Point Digital Signal Processor (Rev. A)

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