TMS320C6713B Floating-Point Digital Signal Processor (Rev. A)
TMS320C6713B Floating-Point Digital Signal Processor (Rev. A)
TMS320C6713B Floating-Point Digital Signal Processor (Rev. A)
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INPUT AND OUTPUT CLOCKS<br />
SPRS294 − OCTOBER 2005<br />
timing requirements for CLKIN for PYP-200 and GDP/ZDP-225 †‡§ (see Figure 31)<br />
NO.<br />
PLL MODE<br />
(PLLEN = 1)<br />
PYP−200<br />
BYPASS MODE<br />
(PLLEN = 0)<br />
PLL MODE<br />
(PLLEN = 1)<br />
GDP/ZDP−225<br />
BYPASS MODE<br />
(PLLEN = 0)<br />
MIN MAX MIN MAX MIN MAX MIN MAX<br />
1 tc(CLKIN) Cycle time, CLKIN 5 83.3 6.7 4.4 83.3 6.7 ns<br />
2 tw(CLKINH) Pulse duration, CLKIN high 0.4C 0.4C 0.4C 0.4C ns<br />
3 tw(CLKINL) Pulse duration, CLKIN low 0.4C 0.4C 0.4C 0.4C ns<br />
4 tt(CLKIN) Transition time, CLKIN 5 5 5 5 ns<br />
† The reference points for the rise and fall transitions are measured at VIL MAX and VIH MIN.<br />
‡ C = CLKIN cycle time in nanoseconds (ns). For example, when CLKIN frequency is 40 MHz, use C = 25 ns.<br />
§ See the PLL and PLL controller section of this data sheet.<br />
UNIT<br />
timing requirements for CLKIN for PYP-225 and GDP/ZDP-300 †‡§ (see Figure 31)<br />
NO.<br />
PLL MODE<br />
(PLLEN = 1)<br />
PYP−225<br />
BYPASS MODE<br />
(PLLEN = 0)<br />
PLL MODE<br />
(PLLEN = 1)<br />
GDP/ZDP−300<br />
BYPASS MODE<br />
(PLLEN = 0)<br />
MIN MAX MIN MAX MIN MAX MIN MAX<br />
1 tc(CLKIN) Cycle time, CLKIN 4.4 83.3 6.7 4 83.3 6.7 ns<br />
2 tw(CLKINH) Pulse duration, CLKIN high 0.4C 0.4C 0.4C 0.4C ns<br />
3 tw(CLKINL) Pulse duration, CLKIN low 0.4C 0.4C 0.4C 0.4C ns<br />
4 tt(CLKIN) Transition time, CLKIN 5 5 5 5 ns<br />
† The reference points for the rise and fall transitions are measured at VIL MAX and VIH MIN.<br />
‡ C = CLKIN cycle time in nanoseconds (ns). For example, when CLKIN frequency is 40 MHz, use C = 25 ns.<br />
§ See the PLL and PLL controller section of this data sheet.<br />
UNIT<br />
timing requirements for CLKIN for PYPA-167, GDPA/ZDPA-200 and PYPA-200 †‡§ (see Figure 31)<br />
NO.<br />
PLL MODE<br />
(PLLEN = 1)<br />
PYPA−167<br />
BYPASS MODE<br />
(PLLEN = 0)<br />
GDPA/ZDPA−200 AND PYPA−200<br />
PLL MODE<br />
(PLLEN = 1)<br />
BYPASS MODE<br />
(PLLEN = 0)<br />
MIN MAX MIN MAX MIN MAX MIN MAX<br />
1 tc(CLKIN) Cycle time, CLKIN 6 83.3 6.7 5 83.3 6.7 ns<br />
2 tw(CLKINH) Pulse duration, CLKIN high 0.4C 0.4C 0.4C 0.4C ns<br />
3 tw(CLKINL) Pulse duration, CLKIN low 0.4C 0.4C 0.4C 0.4C ns<br />
4 tt(CLKIN) Transition time, CLKIN 5 5 5 5 ns<br />
† The reference points for the rise and fall transitions are measured at VIL MAX and VIH MIN.<br />
‡ C = CLKIN cycle time in nanoseconds (ns). For example, when CLKIN frequency is 40 MHz, use C = 25 ns.<br />
§ See the PLL and PLL controller section of this data sheet.<br />
UNIT<br />
2<br />
1<br />
4<br />
CLKIN<br />
3<br />
4<br />
Figure 31. CLKIN Timings<br />
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443<br />
105