TMS320C6713B Floating-Point Digital Signal Processor (Rev. A)

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SPRS294 − OCTOBER 2005 MULTICHANNEL BUFFERED SERIAL PORT TIMING (CONTINUED) CLKS CLKR FSR (int) FSR (ext) DR CLKX 1 4 5 3 3 2 2 3 4 7 3 6 8 Bit(n-1) (n-2) (n-3) FSX (int) 9 FSX (ext) 10 11 FSX (XDATDLY=00b) DX 13 14 13 12 13 Bit 0 Bit(n-1) (n-2) (n-3) Figure 59. McBSP Timings 134 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
MULTICHANNEL BUFFERED SERIAL PORT TIMING (CONTINUED) SPRS294 − OCTOBER 2005 timing requirements for FSR when GSYNC = 1 (see Figure 60) NO. PYP-200,-225 GDP/ZDP -225, -300 PYPA -167, -200 GDPA/ZDPA −200 UNIT MIN MAX 1 tsu(FRH-CKSH) Setup time, FSR high before CLKS high 4 ns 2 th(CKSH-FRH) Hold time, FSR high after CLKS high 4 ns CLKS FSR external CLKR/X (no need to resync) CLKR/X (needs resync) 1 2 Figure 60. FSR Timing When GSYNC = 1 timing requirements for McBSP as SPI master or slave: CLKSTP = 10b, CLKXP = 0 †‡ (see Figure 61) NO. PYP-200,-225 GDP/ZDP -225, -300 PYPA -167, -200 GDPA/ZDPA −200 UNIT MASTER SLAVE MIN MAX MIN MAX 4 tsu(DRV-CKXL) Setup time, DR valid before CLKX low 12 2 − 6P ns 5 th(CKXL-DRV) Hold time, DR valid after CLKX low 4 5 + 12P ns † P = 1/CPU clock frequency in ns. For example, when running parts at 300 MHz, use P = 3.3 ns. ‡ For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1. POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 135
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SPRS294A − OCTOBER 2005 − REVIS
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REVISION HISTORY SPRS294A − OCTOB
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GDP and ZDP 272-Ball BGA package (b
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functional block and CPU (DSP core)
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DEVICE CONFIGURATIONS (CONTINUED) p
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DEVICE CONFIGURATIONS (CONTINUED) S
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MULTIPLEXED PINS NAME PYP GDP/ ZDP
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configuration examples (continued)
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DEVICE CONFIGURATIONS (CONTINUED) S
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SIGNAL NAME PYP PIN NO. GDP/ ZDP TY
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SIGNAL NAME PYP PIN NO. GDP/ ZDP HD
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SIGNAL NAME PYP PIN NO. GDP/ ZDP ED
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SIGNAL NAME PYP PIN NO. GDP/ ZDP TY
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SIGNAL NAME PYP PIN NO. GDP/ ZDP SP
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SIGNAL NAME PYP PIN NO. GDP/ ZDP 11
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VSS SIGNAL NAME PYP PIN NO. GDP/ ZD
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VSS SIGNAL NAME PYP PIN NO. GDP/ ZD
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EDMA module and EDMA selector (cont
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PLL and PLL controller SPRS294A −
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Page 83 and 84: SPRS294A − OCTOBER 2005 − REVIS
Page 85 and 86: multichannel audio serial port (McA
Page 87 and 88: multichannel audio serial port (McA
Page 99 and 100: SPRS294 − OCTOBER 2005 absolute m
Page 101 and 102: PARAMETER MEASUREMENT INFORMATION S
Page 103 and 104: PARAMETER MEASUREMENT INFORMATION (
Page 105 and 106: INPUT AND OUTPUT CLOCKS SPRS294 −
Page 107 and 108: INPUT AND OUTPUT CLOCKS (CONTINUED)
Page 109 and 110: ASYNCHRONOUS MEMORY TIMING (CONTINU
Page 111 and 112: SYNCHRONOUS-BURST MEMORY TIMING tim
Page 113 and 114: SYNCHRONOUS DRAM TIMING timing requ
Page 115 and 116: SYNCHRONOUS DRAM TIMING (CONTINUED)
Page 117 and 118: SYNCHRONOUS DRAM TIMING (CONTINUED)
Page 119 and 120: HOLD/HOLDA TIMING SPRS294 − OCTOB
Page 121 and 122: timing requirements for reset †
Page 123 and 124: EXTERNAL INTERRUPT TIMING SPRS294
Page 125 and 126: MULTICHANNEL AUDIO SERIAL PORT (McA
Page 127 and 128: INTER-INTEGRATED CIRCUITS (I2C) TIM
Page 129 and 130: HOST-PORT INTERFACE TIMING SPRS294
Page 131 and 132: HOST-PORT INTERFACE TIMING (CONTINU
Page 133: MULTICHANNEL BUFFERED SERIAL PORT T
Page 137 and 138: MULTICHANNEL BUFFERED SERIAL PORT T
Page 139 and 140: SPRS294 − OCTOBER 2005 switching
Page 141 and 142: MULTICHANNEL BUFFERED SERIAL PORT T
Page 143 and 144: GENERAL-PURPOSE INPUT/OUTPUT (GPIO)
Page 145 and 146: MECHANICAL DATA SPRS294 − OCTOBER
Page 147 and 148: SPRS294 − OCTOBER 2005 packaging
Page 149 and 150: MECHANICAL DATA MPBG274 - MAY 2002
Page 152: IMPORTANT NOTICE Texas Instruments
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TMS320C6713B Floating-Point Digital Signal Processor (Rev. A)

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