TMS320C6713B Floating-Point Digital Signal Processor (Rev. A)

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SPRS294A − OCTOBER 2005 − REVISED NOVEMBER 2005 multiplexed pins DEVICE CONFIGURATIONS (CONTINUED) Multiplexed pins are pins that are shared by more than one peripheral and are internally multiplexed. Most of these pins are configured by software via the device configuration register (DEVCFG), and the others (specifically, the HPI pins) are configured by external pullup/pulldown resistors only at reset. The muxed pins that are configured by software can be programmed to switch functionalities at any time. The muxed pins that are configured by external pullup/pulldown resistors are mutually exclusive; only one peripheral has primary control of the function of these pins after reset. Table 22 summarizes the peripheral pins affected by the HPI_EN (HD14 pin) and DEVCFG register. Table 23 identifies the multiplexed pins on the device; shows the default (primary) function and the default settings after reset; and describes the pins, registers, etc. necessary to configure the specific multiplexed functions. 36 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
DEVICE CONFIGURATIONS (CONTINUED) SPRS294A − OCTOBER 2005 − REVISED NOVEMBER 2005 SELECTION BITS B I T N A M E HPI_EN (boot config pin) B I T V A L U E 0 MCBSP0DIS (DEVCFG bit) 1 MCBSP1DIS (DEVCFG bit) TOUT0SEL (DEVCFG bit) TOUT1SEL (DEVCFG bit) HD12 (boot config pin) § M M c c A A S S P 0 ‡ P 1 AHCLKX1 AHCLKR1 ACLKX1 ACLKR1 AFSX1 AFSR1 AMUTE1 AXR1[0] to AXR1[7] Table 22. Peripheral Pin Selection Matrix † I 2 C 0 I 2 C 1 PERIPHERAL PINS AVAILABILITY 1 None All 0 None All 0 1 0 ACLKX0 ACLKR0 AFSX0 AFSR0 AHCLKR0 AXR0[0] AXR0[1] NO AMUTE0 AXR0[5] AXR0[6] AXR0[7] AMUTE0 AXR0[5] AXR0[6] AXR0[7] NO AXR0[2] 1 AXR0[2] 0 NO AXR0[4] 1 AXR0[4] 0 1 None All M c B S P 0 None M c B S P 1 All None T I M E R 0 TOUT0 NO TOUT0 T I M E R 1 TOUT1 NO TOUT1 H P I None G P I O P I N S GP[0:1], GP[3], GP[8:15] Plus: GP[2] ctrl’d by GP2EN bit NO GP[0:1], GP[3], GP[8:15] E M I F ED[7:0]; HD8 = 1/0 ED[7:0] side [HD8 = 1 (Little)] ED[31:24] side [HD8 = 0 (Big)] † Gray blocks indicate that the peripheral is not affected by the selection bit. ‡ The McASP0 pins AXR0[3] and AHCLKX0 are shared with the timer input pins TINP0 and TINP1, respectively. See Table 23 for more detailed information. § For more detailed information on endianness correction, see the EMIF Big Endian Mode Correctness portion of this data sheet. POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 37
Page 1 and 2: SPRS294A − OCTOBER 2005 − REVIS
Page 3 and 4: REVISION HISTORY SPRS294A − OCTOB
Page 5 and 6: GDP and ZDP 272-Ball BGA package (b
Page 13 and 14: functional block and CPU (DSP core)
Page 15 and 16: Á Á Á Á Á Á ÁÁÁÁÁ ÁÁÁ
Page 35: DEVICE CONFIGURATIONS (CONTINUED) p
Page 39 and 40: MULTIPLEXED PINS NAME PYP GDP/ ZDP
Page 41 and 42: configuration examples (continued)
Page 47 and 48: DEVICE CONFIGURATIONS (CONTINUED) S
Page 49 and 50: SIGNAL NAME PYP PIN NO. GDP/ ZDP TY
Page 51 and 52: SIGNAL NAME PYP PIN NO. GDP/ ZDP HD
Page 53 and 54: SIGNAL NAME PYP PIN NO. GDP/ ZDP ED
Page 55 and 56: SIGNAL NAME PYP PIN NO. GDP/ ZDP TY
Page 57 and 58: SIGNAL NAME PYP PIN NO. GDP/ ZDP SP
Page 59 and 60: SIGNAL NAME PYP PIN NO. GDP/ ZDP 11
Page 61 and 62: VSS SIGNAL NAME PYP PIN NO. GDP/ ZD
Page 63 and 64: VSS SIGNAL NAME PYP PIN NO. GDP/ ZD
Page 75 and 76: EDMA module and EDMA selector (cont
Page 77 and 78: PLL and PLL controller SPRS294A −
Page 85 and 86: multichannel audio serial port (McA
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multichannel audio serial port (McA
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SPRS294A − OCTOBER 2005 − REVIS
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SPRS294 − OCTOBER 2005 absolute m
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PARAMETER MEASUREMENT INFORMATION S
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PARAMETER MEASUREMENT INFORMATION (
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INPUT AND OUTPUT CLOCKS SPRS294 −
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INPUT AND OUTPUT CLOCKS (CONTINUED)
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ASYNCHRONOUS MEMORY TIMING (CONTINU
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SYNCHRONOUS-BURST MEMORY TIMING tim
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SYNCHRONOUS DRAM TIMING timing requ
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SYNCHRONOUS DRAM TIMING (CONTINUED)
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SYNCHRONOUS DRAM TIMING (CONTINUED)
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HOLD/HOLDA TIMING SPRS294 − OCTOB
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timing requirements for reset †
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EXTERNAL INTERRUPT TIMING SPRS294
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MULTICHANNEL AUDIO SERIAL PORT (McA
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INTER-INTEGRATED CIRCUITS (I2C) TIM
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HOST-PORT INTERFACE TIMING SPRS294
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HOST-PORT INTERFACE TIMING (CONTINU
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MULTICHANNEL BUFFERED SERIAL PORT T
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SPRS294 − OCTOBER 2005 switching
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GENERAL-PURPOSE INPUT/OUTPUT (GPIO)
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MECHANICAL DATA SPRS294 − OCTOBER
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SPRS294 − OCTOBER 2005 packaging
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MECHANICAL DATA MPBG274 - MAY 2002
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IMPORTANT NOTICE Texas Instruments
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TMS320C6713B Floating-Point Digital Signal Processor (Rev. A)

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