TMS320C6713B Floating-Point Digital Signal Processor (Rev. A)

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SPRS294A − OCTOBER 2005 − REVISED NOVEMBER 2005 cache configuration (CCFG) register description The C6713B device includes an enhancement to the cache configuration (CCFG) register. A “P” bit (CCFG.31) allows the programmer to select the priority of accesses to L2 memory originating from the transfer crossbar (TC) over accesses originating from the L1D memory system. An important class of TC accesses is EDMA transfers, which move data to or from the L2 memory. While the EDMA normally has no issue accessing L2 memory due to the high hit rates on the L1D memory system, there are pathological cases where certain CPU behavior could block the EDMA from accessing the L2 memory for long enough to cause a missed deadline when transferring data to a peripheral such as the McASP or McBSP. This can be avoided by setting the P bit to “1” because the EDMA will assume a higher priority than the L1D memory system when accessing L2 memory. For more detailed information on the P-bit function and for silicon advisories concerning EDMA L2 memory accesses blocked, see the TMS320C6713, TMS320C6713B Digital Signal Processors Silicon Errata (literature number SPRZ191). 31 30 10 9 8 7 3 2 0 P † Reserved IP ID Reserved L2MODE R/W-0 R-x W-0 W-0 R-0 0000 R/W-000 Legend: R = Readable; R/W = Readable/Writeable; -n = value after reset; -x = undefined value after reset † This device includes a P bit. Figure 14. Cache Configuration Register (CCFG) Table 25. CCFG Register Bit Field Description BIT # NAME DESCRIPTION L1D requestor priority to L2 bit. 31 P P = 0: L1D requests to L2 higher priority than TC requests P = 1: TC requests to L2 higher priority than L1D requests 30:10 Reserved Reserved. Read-only, writes have no effect. Invalidate L1P bit. 9 IP 0 = Normal L1P operation 1 = All L1P lines are invalidated Invalidate L1D bit. 8 ID 0 = Normal L1D operation 1 = All L1D lines are invalidated 7:3 Reserved Reserved. Read-only, writes have no effect. L2 operation mode bits (L2MODE). 2:0 L2MODE 000b = L2 Cache disabled (All SRAM mode) [256K SRAM] 001b = 1-way Cache (16K L2 Cache) / [240K SRAM] 010b = 2-way Cache (32K L2 Cache) / [224K SRAM] 011b = 3-way Cache (48K L2 Cache) / [208K SRAM] 111b = 4-way Cache (64K L2 Cache) / [192K SRAM] All others Reserved 70 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
SPRS294A − OCTOBER 2005 − REVISED NOVEMBER 2005 interrupts and interrupt selector The C67x DSP core supports 16 prioritized interrupts, which are listed in Table 26. The highest priority interrupt is INT_00 (dedicated to RESET) while the lowest priority is INT_15. The first four interrupts are non-maskable and fixed. The remaining interrupts (4−15) are maskable and default to the interrupt source listed in Table 26. However, their interrupt source may be reprogrammed to any one of the sources listed in Table 27 (Interrupt Selector). Table 27 lists the selector value corresponding to each of the alternate interrupt sources. The selector choice for interrupts 4−15 is made by programming the corresponding fields (listed in Table 26) in the MUXH (address 0x019C0000) and MUXL (address 0x019C0004) registers. POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 71
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SPRS294A − OCTOBER 2005 − REVIS
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REVISION HISTORY SPRS294A − OCTOB
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GDP and ZDP 272-Ball BGA package (b
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functional block and CPU (DSP core)
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Á Á Á Á Á Á ÁÁÁÁÁ ÁÁÁ
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Page 35 and 36: DEVICE CONFIGURATIONS (CONTINUED) p
Page 37 and 38: DEVICE CONFIGURATIONS (CONTINUED) S
Page 39 and 40: MULTIPLEXED PINS NAME PYP GDP/ ZDP
Page 41 and 42: configuration examples (continued)
Page 47 and 48: DEVICE CONFIGURATIONS (CONTINUED) S
Page 49 and 50: SIGNAL NAME PYP PIN NO. GDP/ ZDP TY
Page 51 and 52: SIGNAL NAME PYP PIN NO. GDP/ ZDP HD
Page 53 and 54: SIGNAL NAME PYP PIN NO. GDP/ ZDP ED
Page 55 and 56: SIGNAL NAME PYP PIN NO. GDP/ ZDP TY
Page 57 and 58: SIGNAL NAME PYP PIN NO. GDP/ ZDP SP
Page 59 and 60: SIGNAL NAME PYP PIN NO. GDP/ ZDP 11
Page 61 and 62: VSS SIGNAL NAME PYP PIN NO. GDP/ ZD
Page 63 and 64: VSS SIGNAL NAME PYP PIN NO. GDP/ ZD
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Page 75 and 76: EDMA module and EDMA selector (cont
Page 77 and 78: PLL and PLL controller SPRS294A −
Page 85 and 86: multichannel audio serial port (McA
Page 87 and 88: multichannel audio serial port (McA
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Page 107 and 108: INPUT AND OUTPUT CLOCKS (CONTINUED)
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Page 115 and 116: SYNCHRONOUS DRAM TIMING (CONTINUED)
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timing requirements for reset †
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EXTERNAL INTERRUPT TIMING SPRS294
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MULTICHANNEL AUDIO SERIAL PORT (McA
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INTER-INTEGRATED CIRCUITS (I2C) TIM
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HOST-PORT INTERFACE TIMING SPRS294
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HOST-PORT INTERFACE TIMING (CONTINU
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MULTICHANNEL BUFFERED SERIAL PORT T
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SPRS294 − OCTOBER 2005 switching
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GENERAL-PURPOSE INPUT/OUTPUT (GPIO)
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MECHANICAL DATA SPRS294 − OCTOBER
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SPRS294 − OCTOBER 2005 packaging
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MECHANICAL DATA MPBG274 - MAY 2002
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IMPORTANT NOTICE Texas Instruments
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TMS320C6713B Floating-Point Digital Signal Processor (Rev. A)

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