TMS320C6713B Floating-Point Digital Signal Processor (Rev. A)

HOLD/HOLDA TIMING
SPRS294 − OCTOBER 2005
timing requirements for the HOLD/HOLDA cycles † (see Figure 47)
NO.
PYP-200,-225
GDP/ZDP -225, -300
PYPA -167, -200
GDPA/ZDPA −200
UNIT
MIN MAX
3 th(HOLDAL-HOLDL) Hold time, HOLD low after HOLDA low E ns
† E = ECLKOUT period in ns
switching characteristics over recommended operating conditions for the HOLD/HOLDA cycles †‡
(see Figure 47)
NO.
PARAMETER
PYP-200,-225
GDP/ZDP -225, -300
PYPA -167, -200
GDPA/ZDPA −200
UNIT
MIN MAX
1 td(HOLDL-EMHZ) Delay time, HOLD low to EMIF Bus high impedance 2E § ns
2 td(EMHZ-HOLDAL) Delay time, EMIF Bus high impedance to HOLDA low 0 2E ns
4 td(HOLDH-EMLZ) Delay time, HOLD high to EMIF Bus low impedance 2E 7E ns
5 td(EMLZ-HOLDAH) Delay time, EMIF Bus low impedance to HOLDA high 0 2E ns
† E = ECLKOUT period in ns
‡ EMIF Bus consists of CE[3:0], BE[3:0], ED[31:0], EA[21:2], ARE/SDCAS/SSADS, AOE/SDRAS/SSOE, and AWE/SDWE/SSWE.
§ All pending EMIF transactions are allowed to complete before HOLDA is asserted. If no bus transactions are occurring, then the minimum delay
time can be achieved. Also, bus hold can be indefinitely delayed by setting NOHOLD = 1.
DSP Owns Bus
External Requestor
Owns Bus
DSP Owns Bus
3
HOLD
HOLDA
2 5
EMIF Bus†
C6713B
1
4
C6713B
† EMIF Bus consists of CE[3:0], BE[3:0], ED[31:0], EA[21:2], ARE/SDCAS/SSADS, AOE/SDRAS/SSOE, and AWE/SDWE/SSWE.
Figure 47. HOLD/HOLDA Timing
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