TMS320C6713B Floating-Point Digital Signal Processor (Rev. A)
TMS320C6713B Floating-Point Digital Signal Processor (Rev. A)
TMS320C6713B Floating-Point Digital Signal Processor (Rev. A)
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INTER-INTEGRATED CIRCUITS (I2C) TIMING<br />
timing requirements for I2C timings † (see Figure 53)<br />
NO.<br />
STANDARD<br />
MODE<br />
PYP-200,-225<br />
GDP/ZDP -225, -300<br />
PYPA -167, -200<br />
GDPA/ZDPA −200<br />
SPRS294 − OCTOBER 2005<br />
FAST<br />
MODE<br />
MIN MAX MIN MAX<br />
1 tc(SCL) Cycle time, SCL 10 2.5 µs<br />
2 tsu(SCLH-SDAL)<br />
3 th(SCLL-SDAL)<br />
Setup time, SCL high before SDA low (for a repeated START<br />
condition)<br />
Hold time, SCL low after SDA low (for a START and a repeated<br />
START condition)<br />
UNIT<br />
4.7 0.6 µs<br />
4 0.6 µs<br />
4 tw(SCLL) Pulse duration, SCL low 4.7 1.3 µs<br />
5 tw(SCLH) Pulse duration, SCL high 4 0.6 µs<br />
6 tsu(SDAV-SDLH) Setup time, SDA valid before SCL high 250 100‡ ns<br />
7 th(SDA-SDLL) Hold time, SDA valid after SCL low (For I2C bus devices) 0§ 0§ 0.9 µs<br />
8 tw(SDAH) Pulse duration, SDA high between STOP and START conditions 4.7 1.3 µs<br />
9 tr(SDA) Rise time, SDA 1000 20 + 0.1Cb # 300 ns<br />
10 tr(SCL) Rise time, SCL 1000 20 + 0.1Cb # 300 ns<br />
11 tf(SDA) Fall time, SDA 300 20 + 0.1Cb # 300 ns<br />
12 tf(SCL) Fall time, SCL 300 20 + 0.1Cb # 300 ns<br />
13 tsu(SCLH-SDAH) Setup time, SCL high before SDA high (for STOP condition) 4 0.6 µs<br />
14 tw(SP) Pulse duration, spike (must be suppressed) 0 50 ns<br />
15 Cb # Capacitive load for each bus line 400 400 pF<br />
† The I2C pins SDA and SCL do not feature fail-safe I/O buffers. These pins could potentially draw current when the device is powered down.<br />
‡ A Fast-mode I2C-bus device can be used in a Standard-mode I2C-bus system, but the requirement tsu(SDA−SCLH) ≥ 250 ns must then be met.<br />
This will automatically be the case if the device does not stretch the LOW period of the SCL signal. If such a device does stretch the LOW period<br />
of the SCL signal, it must output the next data bit to the SDA line tr max + tsu(SDA−SCLH) = 1000 + 250 = 1250 ns (according to the Standard-mode<br />
I2C-Bus Specification) before the SCL line is released.<br />
§ A device must internally provide a hold time of at least 300 ns for the SDA signal (referred to the VIHmin of the SCL signal) to bridge the undefined<br />
region of the falling edge of SCL.<br />
The maximum th(SDA−SCLL) has only to be met if the device does not stretch the low period [tw(SCLL)] of the SCL signal.<br />
# Cb = total capacitance of one bus line in pF. If mixed with HS-mode devices, faster fall-times are allowed.<br />
SDA<br />
11 9<br />
8<br />
10<br />
4<br />
5<br />
6 14<br />
13<br />
SCL<br />
3<br />
1<br />
7<br />
12<br />
3<br />
2<br />
Stop Start Repeated<br />
Start<br />
Stop<br />
Figure 53. I 2 C Receive Timings<br />
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443<br />
127
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