TMS320C6713B Floating-Point Digital Signal Processor (Rev. A)
TMS320C6713B Floating-Point Digital Signal Processor (Rev. A)
TMS320C6713B Floating-Point Digital Signal Processor (Rev. A)
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SPRS294A − OCTOBER 2005 − REVISED NOVEMBER 2005<br />
power-down mode logic<br />
Figure 20 shows the power-down mode logic on the C6713B.<br />
CLKOUT2<br />
Internal Clock Tree<br />
Clock<br />
Distribution<br />
and Dividers<br />
PD1<br />
PD2<br />
Clock<br />
PLL<br />
Power-<br />
Down<br />
Logic<br />
PWRD<br />
IFR<br />
IER<br />
CSR<br />
Internal<br />
Peripherals<br />
CPU<br />
PD3<br />
<strong>TMS320C6713B</strong><br />
CLKIN<br />
RESET<br />
† External input clocks, with the exception of CLKIN and CLKOUT3, are not gated by the power-down mode logic.<br />
triggering, wake-up, and effects<br />
Figure 20. Power-Down Mode Logic †<br />
The power-down modes and their wake-up methods are programmed by setting the PWRD field (bits 15−10)<br />
of the control status register (CSR). The PWRD field of the CSR is shown in Figure 21 and described in Table 44.<br />
When writing to the CSR, all bits of the PWRD field should be set at the same time. Logic 0 should be used when<br />
“writing” to the reserved bit (bit 15) of the PWRD field. The CSR is discussed in detail in the TMS320C6000 CPU<br />
and Instruction Set Reference Guide (literature number SPRU189).<br />
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443<br />
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