TMS320C6713B Floating-Point Digital Signal Processor (Rev. A)

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SPRS294A − OCTOBER 2005 − REVISED NOVEMBER 2005 CPU (DSP core) description The <strong>TMS320C6713B</strong> floating-point digital signal processor is based on the C67x CPU. The CPU fetches advanced very-long instruction words (VLIW) (256 bits wide) to supply up to eight 32-bit instructions to the eight functional units during every clock cycle. The VLIW architecture features controls by which all eight units do not have to be supplied with instructions if they are not ready to execute. The first bit of every 32-bit instruction determines if the next instruction belongs to the same execute packet as the previous instruction, or whether it should be executed in the following clock as a part of the next execute packet. Fetch packets are always 256 bits wide; however, the execute packets can vary in size. The variable-length execute packets are a key memory-saving feature, distinguishing the C67x CPU from other VLIW architectures. The CPU features two sets of functional units. Each set contains four units and a register file. One set contains functional units .L1, .S1, .M1, and .D1; the other set contains units .D2, .M2, .S2, and .L2. The two register files each contain 16 32-bit registers for a total of 32 general-purpose registers. The two sets of functional units, along with two register files, compose sides A and B of the CPU (see the functional block and CPU diagram and Figure 1). The four functional units on each side of the CPU can freely share the 16 registers belonging to that side. Additionally, each side features a single data bus connected to all the registers on the other side, by which the two sets of functional units can access data from the register files on the opposite side. While register access by functional units on the same side of the CPU as the register file can service all the units in a single clock cycle, register access using the register file across the CPU supports one read and one write per cycle. The C67x CPU executes all C62x instructions. In addition to C62x fixed-point instructions, the six out of eight functional units (.L1, .S1, .M1, .M2, .S2, and .L2) also execute floating-point instructions. The remaining two functional units (.D1 and .D2) also execute the new LDDW instruction which loads 64 bits per CPU side for a total of 128 bits per cycle. Another key feature of the C67x CPU is the load/store architecture, where all instructions operate on registers (as opposed to data in memory). Two sets of data-addressing units (.D1 and .D2) are responsible for all data transfers between the register files and the memory. The data address driven by the .D units allows data addresses generated from one register file to be used to load or store data to or from the other register file. The C67x CPU supports a variety of indirect addressing modes using either linear- or circular-addressing modes with 5- or 15-bit offsets. All instructions are conditional, and most can access any one of the 32 registers. Some registers, however, are singled out to support specific addressing or to hold the condition for conditional instructions (if the condition is not automatically “true”). The two .M functional units are dedicated for multiplies. The two .S and .L functional units perform a general set of arithmetic, logical, and branch functions with results available every clock cycle. The processing flow begins when a 256-bit-wide instruction fetch packet is fetched from a program memory. The 32-bit instructions destined for the individual functional units are “linked” together by “1” bits in the least significant bit (LSB) position of the instructions. The instructions that are “chained” together for simultaneous execution (up to eight in total) compose an execute packet. A “0” in the LSB of an instruction breaks the chain, effectively placing the instructions that follow it in the next execute packet. If an execute packet crosses the fetch-packet boundary (256 bits wide), the assembler places it in the next fetch packet, while the remainder of the current fetch packet is padded with NOP instructions. The number of execute packets within a fetch packet can vary from one to eight. Execute packets are dispatched to their respective functional units at the rate of one per clock cycle and the next 256-bit fetch packet is not fetched until all the execute packets from the current fetch packet have been dispatched. After decoding, the instructions simultaneously drive all active functional units for a maximum execution rate of eight instructions every clock cycle. While most results are stored in 32-bit registers, they can be subsequently moved to memory as bytes or half-words as well. All load and store instructions are byte-, half-word, or word-addressable. 14 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
Á Á Á Á Á Á ÁÁÁÁÁ ÁÁÁÁÁ SPRS294A − OCTOBER 2005 − REVISED NOVEMBER 2005 CPU (DSP core) description (continued) src1 Á ÁÁÁÁ ÁÁÁÁ .L1† src2 Data Path A LD1 32 MSB ST1 dst long dst long src ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ Á ÁÁÁÁ long src long dst dst .S1† src1 ÁÁÁÁÁ Á ÁÁÁÁ ÁÁÁÁ 8 8 8 src2 Á Á Á Á 8 32 32 ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ Register File A (A0−A15) ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ Á ÁÁÁÁ .M1† ÁÁÁÁ dst src1 Á src2 Á ÁÁÁÁ Á Á ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ LD1 32 LSB DA1 Á ÁÁÁÁ dst src1 src2 ÁÁÁÁÁ ÁÁÁÁ .D1 Á ÁÁÁÁ Á Á ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ 2X DA2 LD2 32 LSB Á Á .D2 src2 src1 dst ÁÁÁÁÁ Á ÁÁÁÁ 1X ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ Á ÁÁÁÁ ÁÁÁÁ src2 ÁÁÁÁÁ .M2† ÁÁÁÁ ÁÁÁÁ src1 dst Á Á Á Á ÁÁÁÁÁ ÁÁÁÁÁ Data Path B LD2 32 MSB ST2 Á Á src2 Á ÁÁÁÁ src1 .S2† dst long dst long src ÁÁÁÁÁ Á ÁÁÁÁ ÁÁÁÁ Á ÁÁÁÁ ÁÁÁÁÁ long src long dst dst .L2† src2 ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ 8 8 8 Á Á 8 32 32 Register File B (B0−B15) ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ src1 Á ÁÁÁÁ Á ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ Á ÁÁÁÁ Control Register File ÁÁÁÁÁ † In addition to fixed-point instructions, these functional units execute floating-point instructions. Figure 1. TMS320C67x CPU (DSP Core) Data Paths Á POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 15
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PARAMETER MEASUREMENT INFORMATION S
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PARAMETER MEASUREMENT INFORMATION (
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INPUT AND OUTPUT CLOCKS SPRS294 −
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INPUT AND OUTPUT CLOCKS (CONTINUED)
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SYNCHRONOUS DRAM TIMING timing requ
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HOLD/HOLDA TIMING SPRS294 − OCTOB
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EXTERNAL INTERRUPT TIMING SPRS294
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MULTICHANNEL AUDIO SERIAL PORT (McA
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MECHANICAL DATA SPRS294 − OCTOBER
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SPRS294 − OCTOBER 2005 packaging
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MECHANICAL DATA MPBG274 - MAY 2002
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IMPORTANT NOTICE Texas Instruments
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TMS320C6713B Floating-Point Digital Signal Processor (Rev. A)

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