TMS320C6713B Floating-Point Digital Signal Processor (Rev. A)

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SPRS294A − OCTOBER 2005 − REVISED NOVEMBER 2005 DEVICE CONFIGURATIONS (CONTINUED) Table 23. C6713B Device Multiplexed/Shared Pins (Continued) NAME MULTIPLEXED PINS PYP GDP/ ZDP DEFAULT FUNCTION DEFAULT SETTING DESCRIPTION TINP1/AHCLKX0 12 F2 Timer 1 input function McASP0PDIR = 0 (input) [specifically AHCLKX bit] By default, the Timer 1 input and McASP0 clock function are enabled as inputs. For the McASP0 clock to function as an output: McASP0PDIR = 1 (specifically the AHCLKX bit] By default, the Timer 1 output pin is enabled. TOUT1/AXR0[4] 13 F1 Timer 1 output function TOUT1SEL = 0 (DEVCFG register bit) [TOUT1 pin enabled and McASP0 AXR0[4] pin disabled] To enable the McASP0 AXR0[4] pin, the TOUT1SEL bit in the DEVCFG register must be set to 1 (disabling the Timer 1 peripheral output pin function). The AXR4 bit in the McASP0PDIR register controls the direction (input/output) of the AXR0[4] pin McASP0PDIR = 0 input, = 1 output configuration examples Figure 6 through Figure 11 illustrate examples of peripheral selections that are configurable on this device. 40 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
configuration examples (continued) DEVICE CONFIGURATIONS (CONTINUED) SPRS294A − OCTOBER 2005 − REVISED NOVEMBER 2005 ED [31:16], ED[15:0] EA[21:2] 32 20 EMIF Clock, System, EMU, and Reset CLKIN, CLKOUT3, CLKMODE0, PLLHV, TMS, TDO, TDI, TCK, TRST, EMU[5:3,1,0], RESET, NMI CE[3:0], BE[3:0], HOLDA, HOLD, BUSREQ, ECLKIN, ECLKOUT, ARE/SDCAS/SSADS, AWE/SDWE/SSWE, AOE/SDRAS/SSOE, ARDY GPIO and EXT_INT GP[15:8, 3:1] GP[0], GP[4](EXT_INT4)/AMUTEIN1, GP[5](EXT_INT5)/AMUTEIN0, GP[6](EXT_INT6), GP[7](EXT_INT7) HPI I2C0 SCL0, SDA0 SCL1, SDA1 I2C1 McASP1 8 AFSX1, AFSR1, ACLKX1, ACLKR1, AHCLKR1, AHCLKX1, AMUTE1 AXR1[7:0] McBSP1 McASP0 8 AXR0[7:0] {TINP0/AXR0[3]} McBSP0 TIMER0 AMUTE0, TINP1/AHCLKX0, AHCLKR0, ACLKR0, ACLKX0, AFSR0, AFSX0 TIMER1 Shading denotes a peripheral module not available for this configuration. DEVCFG Register Value: 0x0000 000F MCBSP0DIS = 1 MCBSP1DIS = 1 TOUT0SEL = 1 TOUT1SEL = 1 EKSRC = 0 HPI_EN(HD14) = 0 GP2EN BIT = 1 (enabling GPEN.[2]) Figure 6. Configuration Example A (2 I2C + 2 McASP + GPIO) POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 41
Page 1 and 2: SPRS294A − OCTOBER 2005 − REVIS
Page 3 and 4: REVISION HISTORY SPRS294A − OCTOB
Page 5 and 6: GDP and ZDP 272-Ball BGA package (b
Page 13 and 14: functional block and CPU (DSP core)
Page 15 and 16: Á Á Á Á Á Á ÁÁÁÁÁ ÁÁÁ
Page 35 and 36: DEVICE CONFIGURATIONS (CONTINUED) p
Page 37 and 38: DEVICE CONFIGURATIONS (CONTINUED) S
Page 39: MULTIPLEXED PINS NAME PYP GDP/ ZDP
Page 43 and 44: configuration examples (continued)
Page 45 and 46: configuration examples (continued)
Page 47 and 48: DEVICE CONFIGURATIONS (CONTINUED) S
Page 49 and 50: SIGNAL NAME PYP PIN NO. GDP/ ZDP TY
Page 51 and 52: SIGNAL NAME PYP PIN NO. GDP/ ZDP HD
Page 53 and 54: SIGNAL NAME PYP PIN NO. GDP/ ZDP ED
Page 55 and 56: SIGNAL NAME PYP PIN NO. GDP/ ZDP TY
Page 57 and 58: SIGNAL NAME PYP PIN NO. GDP/ ZDP SP
Page 59 and 60: SIGNAL NAME PYP PIN NO. GDP/ ZDP 11
Page 61 and 62: VSS SIGNAL NAME PYP PIN NO. GDP/ ZD
Page 63 and 64: VSS SIGNAL NAME PYP PIN NO. GDP/ ZD
Page 75 and 76: EDMA module and EDMA selector (cont
Page 77 and 78: PLL and PLL controller SPRS294A −
Page 85 and 86: multichannel audio serial port (McA
Page 87 and 88: multichannel audio serial port (McA
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SPRS294A − OCTOBER 2005 − REVIS
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SPRS294 − OCTOBER 2005 absolute m
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PARAMETER MEASUREMENT INFORMATION S
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PARAMETER MEASUREMENT INFORMATION (
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INPUT AND OUTPUT CLOCKS SPRS294 −
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INPUT AND OUTPUT CLOCKS (CONTINUED)
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ASYNCHRONOUS MEMORY TIMING (CONTINU
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SYNCHRONOUS-BURST MEMORY TIMING tim
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SYNCHRONOUS DRAM TIMING timing requ
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SYNCHRONOUS DRAM TIMING (CONTINUED)
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SYNCHRONOUS DRAM TIMING (CONTINUED)
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HOLD/HOLDA TIMING SPRS294 − OCTOB
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timing requirements for reset †
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EXTERNAL INTERRUPT TIMING SPRS294
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MULTICHANNEL AUDIO SERIAL PORT (McA
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INTER-INTEGRATED CIRCUITS (I2C) TIM
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HOST-PORT INTERFACE TIMING SPRS294
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HOST-PORT INTERFACE TIMING (CONTINU
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MULTICHANNEL BUFFERED SERIAL PORT T
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SPRS294 − OCTOBER 2005 switching
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GENERAL-PURPOSE INPUT/OUTPUT (GPIO)
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MECHANICAL DATA SPRS294 − OCTOBER
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SPRS294 − OCTOBER 2005 packaging
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MECHANICAL DATA MPBG274 - MAY 2002
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IMPORTANT NOTICE Texas Instruments
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TMS320C6713B Floating-Point Digital Signal Processor (Rev. A)

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