TMS320C6713B Floating-Point Digital Signal Processor (Rev. A)

SPRS294 − OCTOBER 2005
HOST-PORT INTERFACE TIMING (CONTINUED)
HAS
HCNTL[1:0]
HR/W
HHWIL
HSTROBE†
1
1
1
2
2
2
3
1
1
1
4
2
2
2
3
HCS
HD[15:0] (output)
HRDY (case 1)
5
7
1st halfword
15
9
8
16
2nd halfword
6
8
17
HRDY (case 2)
† HSTROBE refers to the following logical operation on HCS, HDS1, and HDS2: [NOT(HDS1 XOR HDS2)] OR HCS.
15
9
17
5
5
Figure 55. HPI Read Timing (HAS Not Used, Tied High)
HAS†
HCNTL[1:0]
10
19 19
11
10
11
HR/W
10
11
10
11
HHWIL
10
11
10
11
HSTROBE‡
HCS
18
3
4
18
HD[15:0] (output)
HRDY (case 1)
5
7
1st half-word
9
8
15
16
2nd half-word
9
17
15
5
HRDY (case 2)
† For correct operation, strobe the HAS signal only once per HSTROBE active cycle.
‡ HSTROBE refers to the following logical operation on HCS, HDS1, and HDS2: [NOT(HDS1 XOR HDS2)] OR HCS.
8
17
5
Figure 56. HPI Read Timing (HAS Used)
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