TMS320C6713B Floating-Point Digital Signal Processor (Rev. A)

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SPRS294A − OCTOBER 2005 − REVISED NOVEMBER 2005 TERMINAL FUNCTIONS The terminal functions table identifies the external signal names, the associated pin (ball) numbers along with the mechanical package designator, the pin type (I, O/Z, or I/O/Z), whether the pin has any internal pullup/pulldown resistors and a functional pin description. For more detailed information on device configuration, peripheral selection, multiplexed/shared pins, and debugging considerations, see the Device Configurations section of this data sheet. SIGNAL NAME PIN NO. GDP/ PYP ZDP TYPE† IPD/ IPU‡ Terminal Functions CLOCK/PLL CONFIGURATION CLKIN 204 A3 I IPD Clock Input DESCRIPTION CLKOUT2/GP[2] 82 Y12 O/Z IPD Clock output at half of device speed (O/Z) [default] (SYSCLK2 internal signal from the clock generator) or this pin can be programmed as GP[2] pin (I/O/Z) CLKOUT3 184 D10 O IPD Clock output programmable by OSCDIV1 register in the PLL controller. Clock generator input clock source select 0 − Reserved, do not use. CLKMODE0 205 C4 I IPU 1 – CLKIN square wave [default] For proper device operation, this pin must be either left unconnected or externally pulled up with a 1-kΩ resistor. PLLHV 202 C5 A Analog power (3.3 V) for PLL (PLL Filter) JTAG EMULATION TMS 192 B7 I IPU JTAG test-port mode select TDO 187 A8 O/Z IPU JTAG test-port data out TDI 191 A7 I IPU JTAG test-port data in TCK 193 A6 I IPU JTAG test-port clock TRST§ 197 B6 I IPD JTAG test-port reset. For IEEE 1149.1 JTAG compatibility, see the IEEE 1149.1 JTAG Compatibility Statement section of this data sheet. EMU5 — B12 I/O/Z IPU Emulation pin 5. Reserved for future use, leave unconnected. EMU4 — C11 I/O/Z IPU Emulation pin 4. Reserved for future use, leave unconnected. EMU3 — B10 I/O/Z IPU Emulation pin 3. Reserved for future use, leave unconnected. EMU2 — D3 I/O/Z IPU Emulation pin 2. Reserved for future use, leave unconnected. EMU1 185 B9 EMU0 186 D9 Emulation [1:0] pins • Select the device functional mode of operation EMU[1:0] Operation 00 Boundary Scan/Functional Mode (see Note) 01 Reserved 10 Reserved 11 Emulation/Functional Mode [default] (see the IEEE 1149.1 I/O/Z IPU JTAG Compatibility Statement section of this data sheet) The DSP can be placed in Functional mode when the EMU[1:0] pins are configured for either Boundary Scan or Emulation. Note: When the EMU[1:0] pins are configured for Boundary Scan mode, the internal pulldown (IPD) on the TRST signal must not be opposed in order to operate in Functional mode. For the Boundary Scan mode drive EMU[1:0] and RESET pins low. † I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal ‡ IPD = Internal pulldown, IPU = Internal pullup. [To oppose the supply rail on these IPD/IPU signal pins, use external pullup or pulldown resistors no greater than 4.4 kΩ and 2.0 kΩ, respectively.] § To ensure a proper logic level during reset when these pins are both routed out and 3−stated or not driven, it is recommended to include an external 10 kΩ pullup/pulldown resistor to sustain the IPU/IPD, respectively. 48 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
SIGNAL NAME PYP PIN NO. GDP/ ZDP TYPE† Terminal Functions (Continued) IPD/ IPU‡ RESET 176 A13 I — NMI 175 C13 I IPD RESETS AND INTERRUPTS SPRS294A − OCTOBER 2005 − REVISED NOVEMBER 2005 DESCRIPTION Device reset. When using Boundary Scan mode, drive the EMU[1:0] and RESET pins low. For this device, this pin does not have an IPU. Nonmaskable interrupt • Edge-driven (rising edge) Any noise on the NMI pin may trigger an NMI interrupt; therefore, if the NMI pin is not used, it is recommended that the NMI pin be grounded versus relying on the IPD. GP[7](EXT_INT7) 7 E3 General-purpose input/output pins (I/O/Z) which also function as external interrupts GP[6](EXT_INT6) 2 D2 • Edge-driven • Polarity independently selected via the External Interrupt Polarity Register GP[5](EXT_INT5)/ AMUTEIN0 6 C1 I/O/Z IPU bits (EXTPOL.[3:0]), in addition to the GPIO registers. GP[4] and GP[5] pins also function as AMUTEIN1 McASP1 mute input and GP[4](EXT_INT4)/ 1 C2 AMUTEIN0 McASP0 mute input, respectively, if enabled by the INEN bit in the AMUTEIN1 associated McASP AMUTE register. HOST-PORT INTERFACE (HPI) HINT/GP[1] 135 J20 O/Z IPU Host interrupt (from DSP to host) (O) [default] or this pin can be programmed as a GP[1] pin (I/O/Z). HCNTL1/AXR1[1] 144 G19 I IPU Host control − selects between control, address, or data registers (I) [default] or McASP1 data pin 1 (I/O/Z). HCNTL0/AXR1[3] 146 G18 I IPU Host control − selects between control, address, or data registers (I) [default] or McASP1 data pin 3 (I/O/Z). HHWIL/AFSR1 139 H20 I IPU Host half-word select − first or second half-word (not necessarily high or low order) (I) [default] or McASP1 receive frame sync or left/right clock (LRCLK) (I/O/Z). HR/W/AXR1[0] 143 G20 I IPU Host read or write select (I) [default] or McASP1 data pin 0 (I/O/Z). † I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal ‡ IPD = Internal pulldown, IPU = Internal pullup. [To oppose the supply rail on these IPD/IPU signal pins, use external pullup or pulldown resistors no greater than 4.4 kΩ and 2.0 kΩ, respectively.] POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 49
Page 1 and 2: SPRS294A − OCTOBER 2005 − REVIS
Page 3 and 4: REVISION HISTORY SPRS294A − OCTOB
Page 5 and 6: GDP and ZDP 272-Ball BGA package (b
Page 13 and 14: functional block and CPU (DSP core)
Page 15 and 16: Á Á Á Á Á Á ÁÁÁÁÁ ÁÁÁ
Page 35 and 36: DEVICE CONFIGURATIONS (CONTINUED) p
Page 37 and 38: DEVICE CONFIGURATIONS (CONTINUED) S
Page 39 and 40: MULTIPLEXED PINS NAME PYP GDP/ ZDP
Page 41 and 42: configuration examples (continued)
Page 47: DEVICE CONFIGURATIONS (CONTINUED) S
Page 51 and 52: SIGNAL NAME PYP PIN NO. GDP/ ZDP HD
Page 53 and 54: SIGNAL NAME PYP PIN NO. GDP/ ZDP ED
Page 55 and 56: SIGNAL NAME PYP PIN NO. GDP/ ZDP TY
Page 57 and 58: SIGNAL NAME PYP PIN NO. GDP/ ZDP SP
Page 59 and 60: SIGNAL NAME PYP PIN NO. GDP/ ZDP 11
Page 61 and 62: VSS SIGNAL NAME PYP PIN NO. GDP/ ZD
Page 63 and 64: VSS SIGNAL NAME PYP PIN NO. GDP/ ZD
Page 75 and 76: EDMA module and EDMA selector (cont
Page 77 and 78: PLL and PLL controller SPRS294A −
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Page 87 and 88: multichannel audio serial port (McA
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SPRS294 − OCTOBER 2005 absolute m
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PARAMETER MEASUREMENT INFORMATION S
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PARAMETER MEASUREMENT INFORMATION (
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INPUT AND OUTPUT CLOCKS SPRS294 −
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INPUT AND OUTPUT CLOCKS (CONTINUED)
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ASYNCHRONOUS MEMORY TIMING (CONTINU
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SYNCHRONOUS-BURST MEMORY TIMING tim
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SYNCHRONOUS DRAM TIMING timing requ
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SYNCHRONOUS DRAM TIMING (CONTINUED)
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SYNCHRONOUS DRAM TIMING (CONTINUED)
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HOLD/HOLDA TIMING SPRS294 − OCTOB
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timing requirements for reset †
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EXTERNAL INTERRUPT TIMING SPRS294
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MULTICHANNEL AUDIO SERIAL PORT (McA
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INTER-INTEGRATED CIRCUITS (I2C) TIM
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HOST-PORT INTERFACE TIMING SPRS294
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HOST-PORT INTERFACE TIMING (CONTINU
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MULTICHANNEL BUFFERED SERIAL PORT T
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SPRS294 − OCTOBER 2005 switching
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GENERAL-PURPOSE INPUT/OUTPUT (GPIO)
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MECHANICAL DATA SPRS294 − OCTOBER
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SPRS294 − OCTOBER 2005 packaging
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MECHANICAL DATA MPBG274 - MAY 2002
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IMPORTANT NOTICE Texas Instruments
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TMS320C6713B Floating-Point Digital Signal Processor (Rev. A)

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