TMS320C6713B Floating-Point Digital Signal Processor (Rev. A)
TMS320C6713B Floating-Point Digital Signal Processor (Rev. A)
TMS320C6713B Floating-Point Digital Signal Processor (Rev. A)
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SPRS294A − OCTOBER 2005 − REVISED NOVEMBER 2005<br />
cache configuration (CCFG) register description<br />
The C6713B device includes an enhancement to the cache configuration (CCFG) register. A “P” bit<br />
(CCFG.31) allows the programmer to select the priority of accesses to L2 memory originating from the transfer<br />
crossbar (TC) over accesses originating from the L1D memory system. An important class of TC accesses is<br />
EDMA transfers, which move data to or from the L2 memory. While the EDMA normally has no issue accessing<br />
L2 memory due to the high hit rates on the L1D memory system, there are pathological cases where certain<br />
CPU behavior could block the EDMA from accessing the L2 memory for long enough to cause a missed deadline<br />
when transferring data to a peripheral such as the McASP or McBSP. This can be avoided by setting the P bit<br />
to “1” because the EDMA will assume a higher priority than the L1D memory system when accessing L2<br />
memory.<br />
For more detailed information on the P-bit function and for silicon advisories concerning EDMA L2 memory<br />
accesses blocked, see the TMS320C6713, <strong>TMS320C6713B</strong> <strong>Digital</strong> <strong>Signal</strong> <strong>Processor</strong>s Silicon Errata (literature<br />
number SPRZ191).<br />
31 30 10 9 8 7 3 2 0<br />
P † Reserved IP ID Reserved L2MODE<br />
R/W-0 R-x W-0 W-0 R-0 0000 R/W-000<br />
Legend: R = Readable; R/W = Readable/Writeable; -n = value after reset; -x = undefined value after reset<br />
† This device includes a P bit.<br />
Figure 14. Cache Configuration Register (CCFG)<br />
Table 25. CCFG Register Bit Field Description<br />
BIT # NAME DESCRIPTION<br />
L1D requestor priority to L2 bit.<br />
31 P P = 0: L1D requests to L2 higher priority than TC requests<br />
P = 1: TC requests to L2 higher priority than L1D requests<br />
30:10 Reserved Reserved. Read-only, writes have no effect.<br />
Invalidate L1P bit.<br />
9 IP 0 = Normal L1P operation<br />
1 = All L1P lines are invalidated<br />
Invalidate L1D bit.<br />
8 ID 0 = Normal L1D operation<br />
1 = All L1D lines are invalidated<br />
7:3 Reserved Reserved. Read-only, writes have no effect.<br />
L2 operation mode bits (L2MODE).<br />
2:0 L2MODE<br />
000b = L2 Cache disabled (All SRAM mode) [256K SRAM]<br />
001b = 1-way Cache (16K L2 Cache) / [240K SRAM]<br />
010b = 2-way Cache (32K L2 Cache) / [224K SRAM]<br />
011b = 3-way Cache (48K L2 Cache) / [208K SRAM]<br />
111b = 4-way Cache (64K L2 Cache) / [192K SRAM]<br />
All others Reserved<br />
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