TMS320C6713B Floating-Point Digital Signal Processor (Rev. A)
TMS320C6713B Floating-Point Digital Signal Processor (Rev. A)
TMS320C6713B Floating-Point Digital Signal Processor (Rev. A)
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SPRS294 − OCTOBER 2005<br />
SYNCHRONOUS-BURST MEMORY TIMING (CONTINUED)<br />
ECLKOUT<br />
CEx<br />
BE[3:0]<br />
EA[21:2]<br />
ED[31:0]<br />
ARE/SDCAS/SSADS†<br />
AOE/SDRAS/SSOE†<br />
AWE/SDWE/SSWE†<br />
1<br />
1<br />
2<br />
3<br />
BE1 BE2 BE3 BE4<br />
4<br />
5<br />
EA<br />
6<br />
7<br />
Q1 Q2 Q3 Q4<br />
8 8<br />
9<br />
9<br />
† ARE/SDCAS/SSADS, AOE/SDRAS/SSOE, and AWE/SDWE/SSWE operate as SSADS, SSOE, and SSWE, respectively, during SBSRAM<br />
accesses.<br />
Figure 38. SBSRAM Read Timing<br />
ECLKOUT<br />
CEx<br />
BE[3:0]<br />
EA[21:2]<br />
ED[31:0]<br />
1<br />
2<br />
BE1 BE2 BE3 BE4<br />
4<br />
5<br />
EA<br />
10<br />
Q1 Q2 Q3 Q4<br />
1<br />
3<br />
11<br />
ARE/SDCAS/SSADS†<br />
AOE/SDRAS/SSOE†<br />
8<br />
8<br />
AWE/SDWE/SSWE†<br />
12<br />
12<br />
† ARE/SDCAS/SSADS, AOE/SDRAS/SSOE, and AWE/SDWE/SSWE operate as SSADS, SSOE, and SSWE, respectively, during SBSRAM<br />
accesses.<br />
Figure 39. SBSRAM Write Timing<br />
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