TMS320C6713B Floating-Point Digital Signal Processor (Rev. A)

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SPRS294A − OCTOBER 2005 − REVISED NOVEMBER 2005 memory map summary Table 3 shows the memory map address ranges of the device. Table 3. Memory Map Summary MEMORY BLOCK DESCRIPTION BLOCK SIZE (BYTES) HEX ADDRESS RANGE Internal RAM (L2) 192K 0000 0000 – 0002 FFFF Internal RAM/Cache 64K 0003 0000 – 0003 FFFF Reserved 24M – 256K 0004 0000 – 017F FFFF External Memory Interface (EMIF) Registers 256K 0180 0000 – 0183 FFFF L2 Registers 128K 0184 0000 – 0185 FFFF Reserved 128K 0186 0000 – 0187 FFFF HPI Registers 256K 0188 0000 – 018B FFFF McBSP 0 Registers 256K 018C 0000 – 018F FFFF McBSP 1 Registers 256K 0190 0000 – 0193 FFFF Timer 0 Registers 256K 0194 0000 – 0197 FFFF Timer 1 Registers 256K 0198 0000 – 019B FFFF Interrupt Selector Registers 512 019C 0000 – 019C 01FF Device Configuration Registers 4 019C 0200 – 019C 0203 Reserved 256K − 516 019C 0204 – 019F FFFF EDMA RAM and EDMA Registers 256K 01A0 0000 – 01A3 FFFF Reserved 768K 01A4 0000 – 01AF FFFF GPIO Registers 16K 01B0 0000 – 01B0 3FFF Reserved 240K 01B0 4000 – 01B3 FFFF I2C0 Registers 16K 01B4 0000 – 01B4 3FFF I2C1 Registers 16K 01B4 4000 – 01B4 7FFF Reserved 16K 01B4 8000 – 01B4 BFFF McASP0 Registers 16K 01B4 C000 – 01B4 FFFF McASP1 Registers 16K 01B5 0000 – 01B5 3FFF Reserved 160K 01B5 4000 – 01B7 BFFF PLL Registers 8K 01B7 C000 – 01B7 DFFF Reserved 264K 01B7 E000 – 01BB FFFF Emulation Registers 256K 01BC 0000 – 01BF FFFF Reserved 4M 01C0 0000 – 01FF FFFF QDMA Registers 52 0200 0000 – 0200 0033 Reserved 16M − 52 0200 0034 – 02FF FFFF Reserved 720M 0300 0000 – 2FFF FFFF McBSP0 Data Port 64M 3000 0000 – 33FF FFFF McBSP1 Data Port 64M 3400 0000 – 37FF FFFF Reserved 64M 3800 0000 – 3BFF FFFF McASP0 Data Port 1M 3C00 0000 – 3C0F FFFF McASP1 Data Port 1M 3C10 0000 – 3C1F FFFF Reserved 1G + 62M 3C20 0000 – 7FFF FFFF EMIF CE0 † 256M 8000 0000 – 8FFF FFFF EMIF CE1 † 256M 9000 0000 – 9FFF FFFF EMIF CE2 † 256M A000 0000 – AFFF FFFF EMIF CE3 † 256M B000 0000 – BFFF FFFF Reserved 1G C000 0000 – FFFF FFFF † The number of EMIF address pins (EA[21:2]) limits the maximum addressable memory (SDRAM) to 128MB per CE space. 16 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
SPRS294A − OCTOBER 2005 − REVISED NOVEMBER 2005 L2 memory structure expanded Figure 2 shows the detail of the L2 memory structure. L2 Mode L2 Memory Block Base Address 000 001 010 011 111 0x0000 0000 256K SRAM (All) 240K SRAM 224K SRAM 208K SRAM 192K SRAM 192K-Byte RAM 16K-Byte RAM 0x0003 0000 16K 1-Way Cache 32K 2-Way Cache 48K 3-Way Cache 64K 4-Way Cache ÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎ 16K-Byte RAM ÎÎÎÎÎÎÎÎÎÎ 16K-Byte RAM 16K-Byte RAM 0x0003 4000 0x0003 8000 0x0003 C000 0x0003 FFFF Figure 2. L2 Memory Configuration POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 17
Page 1 and 2: SPRS294A − OCTOBER 2005 − REVIS
Page 3 and 4: REVISION HISTORY SPRS294A − OCTOB
Page 5 and 6: GDP and ZDP 272-Ball BGA package (b
Page 13 and 14: functional block and CPU (DSP core)
Page 15: Á Á Á Á Á Á ÁÁÁÁÁ ÁÁÁ
Page 35 and 36: DEVICE CONFIGURATIONS (CONTINUED) p
Page 37 and 38: DEVICE CONFIGURATIONS (CONTINUED) S
Page 39 and 40: MULTIPLEXED PINS NAME PYP GDP/ ZDP
Page 41 and 42: configuration examples (continued)
Page 47 and 48: DEVICE CONFIGURATIONS (CONTINUED) S
Page 49 and 50: SIGNAL NAME PYP PIN NO. GDP/ ZDP TY
Page 51 and 52: SIGNAL NAME PYP PIN NO. GDP/ ZDP HD
Page 53 and 54: SIGNAL NAME PYP PIN NO. GDP/ ZDP ED
Page 55 and 56: SIGNAL NAME PYP PIN NO. GDP/ ZDP TY
Page 57 and 58: SIGNAL NAME PYP PIN NO. GDP/ ZDP SP
Page 59 and 60: SIGNAL NAME PYP PIN NO. GDP/ ZDP 11
Page 61 and 62: VSS SIGNAL NAME PYP PIN NO. GDP/ ZD
Page 63 and 64: VSS SIGNAL NAME PYP PIN NO. GDP/ ZD
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SPRS294A − OCTOBER 2005 − REVIS
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EDMA module and EDMA selector (cont
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PLL and PLL controller SPRS294A −
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multichannel audio serial port (McA
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multichannel audio serial port (McA
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SPRS294 − OCTOBER 2005 absolute m
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PARAMETER MEASUREMENT INFORMATION S
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PARAMETER MEASUREMENT INFORMATION (
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INPUT AND OUTPUT CLOCKS SPRS294 −
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INPUT AND OUTPUT CLOCKS (CONTINUED)
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ASYNCHRONOUS MEMORY TIMING (CONTINU
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SYNCHRONOUS-BURST MEMORY TIMING tim
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SYNCHRONOUS DRAM TIMING timing requ
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SYNCHRONOUS DRAM TIMING (CONTINUED)
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SYNCHRONOUS DRAM TIMING (CONTINUED)
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HOLD/HOLDA TIMING SPRS294 − OCTOB
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timing requirements for reset †
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EXTERNAL INTERRUPT TIMING SPRS294
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MULTICHANNEL AUDIO SERIAL PORT (McA
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INTER-INTEGRATED CIRCUITS (I2C) TIM
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HOST-PORT INTERFACE TIMING SPRS294
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HOST-PORT INTERFACE TIMING (CONTINU
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MULTICHANNEL BUFFERED SERIAL PORT T
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SPRS294 − OCTOBER 2005 switching
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GENERAL-PURPOSE INPUT/OUTPUT (GPIO)
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MECHANICAL DATA SPRS294 − OCTOBER
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SPRS294 − OCTOBER 2005 packaging
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MECHANICAL DATA MPBG274 - MAY 2002
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IMPORTANT NOTICE Texas Instruments
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TMS320C6713B Floating-Point Digital Signal Processor (Rev. A)

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