TMS320C6713B Floating-Point Digital Signal Processor (Rev. A)
TMS320C6713B Floating-Point Digital Signal Processor (Rev. A)
TMS320C6713B Floating-Point Digital Signal Processor (Rev. A)
Create successful ePaper yourself
Turn your PDF publications into a flip-book with our unique Google optimized e-Paper software.
SPRS294A − OCTOBER 2005 − REVISED NOVEMBER 2005<br />
TYPE<br />
Table 45. C6713B Example Boards and Maximum EMIF Speed<br />
BOARD CONFIGURATION<br />
EMIF INTERFACE<br />
COMPONENTS<br />
BOARD TRACE<br />
SDRAM SPEED GRADE<br />
143 MHz 32-bit SDRAM (−7) 100 MHz<br />
MAXIMUM ACHIEVABLE<br />
EMIF-SDRAM<br />
INTERFACE SPEED<br />
1 to 3-inch traces with proper 166 MHz 32-bit SDRAM (−6) For short traces, SDRAM data<br />
1-Load<br />
One bank of one<br />
termination resistors;<br />
output hold time on these<br />
Short Traces 32-Bit SDRAM<br />
Trace impedance ~ 50 Ω<br />
183 MHz 32-bit SDRAM (−55) SDRAM speed grades cannot<br />
meet EMIF input hold time<br />
200 MHz 32-bit SDRAM (−5) requirement (see NOTE 1).<br />
125 MHz 16-bit SDRAM (−8E) 100 MHz<br />
1.2 to 3 inches from EMIF to 133 MHz 16-bit SDRAM (−75) 100 MHz<br />
2-Loads<br />
Short Traces One bank of two<br />
16-Bit SDRAMs each load, with proper<br />
termination resistors;<br />
143 MHz 16-bit SDRAM (−7E) 100 MHz<br />
Trace impedance ~ 78 Ω 167 MHz 16-bit SDRAM (−6A) 100 MHz<br />
167 MHz 16-bit SDRAM (−6) 100 MHz<br />
125 MHz 16-bit SDRAM (−8E)<br />
For short traces, EMIF cannot<br />
meet SDRAM input hold<br />
requirement (see NOTE 1).<br />
1.2 to 3 inches from EMIF to<br />
One bank of two<br />
133 MHz 16-bit SDRAM (−75) 100 MHz<br />
3-Loads<br />
each load, with proper<br />
32-Bit SDRAMs<br />
143 MHz 16-bit SDRAM (−7E) 100 MHz<br />
Short Traces<br />
termination resistors;<br />
One bank of buffer<br />
Trace impedance ~ 78 Ω 167 MHz 16-bit SDRAM (−6A) 100 MHz<br />
For short traces, EMIF cannot<br />
167 MHz 16-bit SDRAM (−6) meet SDRAM input hold<br />
requirement (see NOTE 1).<br />
143 MHz 32-bit SDRAM (−7) 83 MHz<br />
One bank of one<br />
166 MHz 32-bit SDRAM (−6) 83 MHz<br />
32-Bit SDRAM<br />
3-Loads<br />
4 to 7 inches from EMIF;<br />
One bank of one<br />
183 MHz 32-bit SDRAM (−55) 83 MHz<br />
Long Traces<br />
Trace impedance ~ 63 Ω<br />
32-Bit SBSRAM<br />
SDRAM data output hold time<br />
One bank of buffer<br />
200 MHz 32-bit SDRAM (−5) cannot meet EMIF input hold<br />
requirement (see NOTE 1).<br />
NOTE 1: Results are based on IBIS simulations for the given example boards (TYPE). Timing analysis should be performed to determine if timing<br />
requirements can be met for the particular system.<br />
96 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
Change language