TMS320C6713B Floating-Point Digital Signal Processor (Rev. A)

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SPRS294A − OCTOBER 2005 − REVISED NOVEMBER 2005 TYPE Table 45. C6713B Example Boards and Maximum EMIF Speed BOARD CONFIGURATION EMIF INTERFACE COMPONENTS BOARD TRACE SDRAM SPEED GRADE 143 MHz 32-bit SDRAM (−7) 100 MHz MAXIMUM ACHIEVABLE EMIF-SDRAM INTERFACE SPEED 1 to 3-inch traces with proper 166 MHz 32-bit SDRAM (−6) For short traces, SDRAM data 1-Load One bank of one termination resistors; output hold time on these Short Traces 32-Bit SDRAM Trace impedance ~ 50 Ω 183 MHz 32-bit SDRAM (−55) SDRAM speed grades cannot meet EMIF input hold time 200 MHz 32-bit SDRAM (−5) requirement (see NOTE 1). 125 MHz 16-bit SDRAM (−8E) 100 MHz 1.2 to 3 inches from EMIF to 133 MHz 16-bit SDRAM (−75) 100 MHz 2-Loads Short Traces One bank of two 16-Bit SDRAMs each load, with proper termination resistors; 143 MHz 16-bit SDRAM (−7E) 100 MHz Trace impedance ~ 78 Ω 167 MHz 16-bit SDRAM (−6A) 100 MHz 167 MHz 16-bit SDRAM (−6) 100 MHz 125 MHz 16-bit SDRAM (−8E) For short traces, EMIF cannot meet SDRAM input hold requirement (see NOTE 1). 1.2 to 3 inches from EMIF to One bank of two 133 MHz 16-bit SDRAM (−75) 100 MHz 3-Loads each load, with proper 32-Bit SDRAMs 143 MHz 16-bit SDRAM (−7E) 100 MHz Short Traces termination resistors; One bank of buffer Trace impedance ~ 78 Ω 167 MHz 16-bit SDRAM (−6A) 100 MHz For short traces, EMIF cannot 167 MHz 16-bit SDRAM (−6) meet SDRAM input hold requirement (see NOTE 1). 143 MHz 32-bit SDRAM (−7) 83 MHz One bank of one 166 MHz 32-bit SDRAM (−6) 83 MHz 32-Bit SDRAM 3-Loads 4 to 7 inches from EMIF; One bank of one 183 MHz 32-bit SDRAM (−55) 83 MHz Long Traces Trace impedance ~ 63 Ω 32-Bit SBSRAM SDRAM data output hold time One bank of buffer 200 MHz 32-bit SDRAM (−5) cannot meet EMIF input hold requirement (see NOTE 1). NOTE 1: Results are based on IBIS simulations for the given example boards (TYPE). Timing analysis should be performed to determine if timing requirements can be met for the particular system. 96 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
SPRS294A − OCTOBER 2005 − REVISED NOVEMBER 2005 EMIF big endian mode correctness The HD8 pin device endian mode (LENDIAN) selects the endian mode of operation (Little or Big Endian). For the C6713B device Little Endian is the default setting. The HD12 pin (EMIF Big Endian Mode Correctness) [EMIFBE] enhancement allows the flexibility to change the EMIF data placement on the EMIF bus. When using the default setting of HD12 = 1 for the C6713B, the EMIF will present 8-bit or 16-bit data on the ED[7:0] side of the bus if using Little Endian mode (HD8 = 1) and to the ED[31:24] side of the bus if using Big Endian mode. Figure 23 shows the mapping of 16-bit and 8-bit C6713B devices. EMIF DATA LINES (PINS) WHERE DATA PRESENT ED[31:24] (BE3) ED[23:16] (BE2) ED[15:8] (BE1) ED[7:0] (BE0) 16-Bit Device in Big Endianness Mode 8-Bit Device in Big Endianness Mode 32-Bit Device in Any Endianness Mode 16-Bit Device in Little Endianness Mode Figure 23. 16/8-Bit EMIF Big Endian Mode Correctness Mapping (HD12 = 1) 8-Bit Device in Little Endianness Mode When HD12 = 0, enabling EMIF endianness correction, the EMIF will present 8-bit or 16-bit data on the ED[7:0] side of the bus, regardless of the endianess mode (see Figure 24). EMIF DATA LINES (PINS) WHERE DATA PRESENT ED[31:24] (BE3) ED[23:16] (BE2) ED[15:8] (BE1) ED[7:0] (BE0) 32-Bit Device in Any Endianness Mode 16-Bit Device in Any Endianness Mode 8-Bit Device in Any Endianness Mode Figure 24. 16/8-Bit EMIF Big Endian Mode Correctness Mapping (HD12 = 0) This new endianness correction functionality does not affect systems using the default value of HD12 = 1. This new feature does not affect systems operating in Little Endian mode. POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 97
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SPRS294A − OCTOBER 2005 − REVIS
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REVISION HISTORY SPRS294A − OCTOB
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GDP and ZDP 272-Ball BGA package (b
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functional block and CPU (DSP core)
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DEVICE CONFIGURATIONS (CONTINUED) p
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DEVICE CONFIGURATIONS (CONTINUED) S
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MULTIPLEXED PINS NAME PYP GDP/ ZDP
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configuration examples (continued)
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configuration examples (continued)
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Page 49 and 50: SIGNAL NAME PYP PIN NO. GDP/ ZDP TY
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Page 53 and 54: SIGNAL NAME PYP PIN NO. GDP/ ZDP ED
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Page 61 and 62: VSS SIGNAL NAME PYP PIN NO. GDP/ ZD
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SPRS294 − OCTOBER 2005 packaging
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MECHANICAL DATA MPBG274 - MAY 2002
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IMPORTANT NOTICE Texas Instruments
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TMS320C6713B Floating-Point Digital Signal Processor (Rev. A)

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