TMS320C6713B Floating-Point Digital Signal Processor (Rev. A)

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SPRS294A − OCTOBER 2005 − REVISED NOVEMBER 2005 PAGE(S) NO. ADDITIONS/CHANGES/DELETIONS 95 IEEE 1149.1 JTAG Compatibility Statement section: Updated/added paragraphs for clarity 99 Recommended Operating Conditions: Added VOS, Maximum voltage during overshoot row and associated footnote Added VUS, Maximum voltage during undershoot row and associated footnote 102 Parameter Measurement Information, AC transient rise/fall time specifications section: Added AC Transient Specification Rise Time figure Added AC Transient Specification Fall Time figure 124 MULTICHANNEL AUDIO SERIAL PORT (McASP) TIMING: timing requirements for McASP section: Updated Parameter No. 3, tc(ACKRX), from “33” to “greater of 2P or 33 ns” and added associated footnote 124 MULTICHANNEL AUDIO SERIAL PORT (McASP) TIMING: switching characteristics over recommended operating conditions for McASP section: Updated Parameter No. 11, tc(ACKRX), from “33” to “greater of 2P or 33 ns” and added associated footnote 125, 126 MULTICHANNEL AUDIO SERIAL PORT (McASP) TIMING section: Updated McASP Input and Output drawings 134 MULTICHANNEL BUFFERED SERIAL PORT TIMING section: switching characteristics over recommended operating conditions for McBSP section: Updated McBSP Timings figure 147 Mechanical Data section: Added statement to the Packaging Information section 4 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
GDP and ZDP 272-Ball BGA package (bottom view) SPRS294A − OCTOBER 2005 − REVISED NOVEMBER 2005 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 5
Page 1 and 2: SPRS294A − OCTOBER 2005 − REVIS
Page 3: REVISION HISTORY SPRS294A − OCTOB
Page 13 and 14: functional block and CPU (DSP core)
Page 15 and 16: Á Á Á Á Á Á ÁÁÁÁÁ ÁÁÁ
Page 35 and 36: DEVICE CONFIGURATIONS (CONTINUED) p
Page 37 and 38: DEVICE CONFIGURATIONS (CONTINUED) S
Page 39 and 40: MULTIPLEXED PINS NAME PYP GDP/ ZDP
Page 41 and 42: configuration examples (continued)
Page 47 and 48: DEVICE CONFIGURATIONS (CONTINUED) S
Page 49 and 50: SIGNAL NAME PYP PIN NO. GDP/ ZDP TY
Page 51 and 52: SIGNAL NAME PYP PIN NO. GDP/ ZDP HD
Page 53 and 54: SIGNAL NAME PYP PIN NO. GDP/ ZDP ED
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SIGNAL NAME PYP PIN NO. GDP/ ZDP TY
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SIGNAL NAME PYP PIN NO. GDP/ ZDP SP
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SIGNAL NAME PYP PIN NO. GDP/ ZDP 11
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VSS SIGNAL NAME PYP PIN NO. GDP/ ZD
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VSS SIGNAL NAME PYP PIN NO. GDP/ ZD
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SPRS294A − OCTOBER 2005 − REVIS
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EDMA module and EDMA selector (cont
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PLL and PLL controller SPRS294A −
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multichannel audio serial port (McA
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multichannel audio serial port (McA
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SPRS294 − OCTOBER 2005 absolute m
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PARAMETER MEASUREMENT INFORMATION S
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PARAMETER MEASUREMENT INFORMATION (
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INPUT AND OUTPUT CLOCKS SPRS294 −
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INPUT AND OUTPUT CLOCKS (CONTINUED)
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ASYNCHRONOUS MEMORY TIMING (CONTINU
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SYNCHRONOUS-BURST MEMORY TIMING tim
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SYNCHRONOUS DRAM TIMING timing requ
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SYNCHRONOUS DRAM TIMING (CONTINUED)
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SYNCHRONOUS DRAM TIMING (CONTINUED)
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HOLD/HOLDA TIMING SPRS294 − OCTOB
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timing requirements for reset †
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EXTERNAL INTERRUPT TIMING SPRS294
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MULTICHANNEL AUDIO SERIAL PORT (McA
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INTER-INTEGRATED CIRCUITS (I2C) TIM
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HOST-PORT INTERFACE TIMING SPRS294
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HOST-PORT INTERFACE TIMING (CONTINU
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MULTICHANNEL BUFFERED SERIAL PORT T
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SPRS294 − OCTOBER 2005 switching
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GENERAL-PURPOSE INPUT/OUTPUT (GPIO)
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MECHANICAL DATA SPRS294 − OCTOBER
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SPRS294 − OCTOBER 2005 packaging
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MECHANICAL DATA MPBG274 - MAY 2002
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IMPORTANT NOTICE Texas Instruments
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TMS320C6713B Floating-Point Digital Signal Processor (Rev. A)

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