TMS320C6713B Floating-Point Digital Signal Processor (Rev. A)

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SPRS294A − OCTOBER 2005 − REVISED NOVEMBER 2005 PYP PowerPAD QFP package (top view) PYP 208-PIN PowerPAD PLASTIC QUAD FLATPACK (PQFP) ( TOP VIEW ) HD4/GP[0] HD2/AFSX1 HD3/AMUTE1 HAS/ACLKX1 HD1/AXR1[7] HDS1/AXR1[6] HDS2/AXR1[5] CV DD VSS HD0/AXR1[4] HCNTL0/AXR1[3] HCS/AXR1[2] HCNTL1/AXR1[1] HR/ W/AXR1[0] VSS DV DD HRDY/ACLKR1 HHWIL/AFSR1 HOLD HOLDA BUSREQ HINT /GP[1] V SS CVDD ED0 ED1 ED2 ED3 ED5 ED4 DV DD VSS CVDD ED8 ED7 ED6 ED10 ED9 ED12 ED11 CV DD VSS DV DD ED14 ED15 ED13 BE0 EA21 BE1 DVDD VSS CV DD CV DD V SS HD5/AHCLKX1 HD8/GP[8] HD6/AHCLKR1 DV DD V SS HD7/GP[3] HD9/GP[9] HD10/GP[10] HD11/GP[11] HD12/GP[12] CV DD V SS CV DD HD13/GP[13] HD14/GP[14] HD15/GP[15] NMI RESET CVDD RSV RSV RSV RSV V SS DV DD CLKOUT3 EMU1 EMU0 TDO DV DD V SS CV DD TDI TMS TCK V SS CV DD CV DD TRST RSV V SS RSV CV DD PLLHV V SS CLKIN CLKMODE0 DV DD V SS CV DD 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 156 155 154 153 152 151 150 149 148 147 146 145 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 8,30 6,79 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 1 2 3 4 5 6 7 8 9 8,30 6,79 Exposed Thermal PAD 42 43 44 45 46 47 48 49 50 51 52 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 CV DD CE1 CE0 EA20 EA19 EA17 DV DD V SS CV DD EA18 EA15 EA12 EA16 EA13 EA14 CV DD V SS DV DD EA11 V SS DV DD AWE/SDWE/SSWE CLKOUT2/GP[2] V SS CV DD ARE/SDCAS/SSADS ECLKIN ECLKOUT EA10 AOE/SDRAS/SSOE EA9 V SS DV DD EA8 EA7 EA6 EA5 CV DD V SS DV DD EA4 EA3 EA2 CE2 CV DD V SS DV DD CE3 ARDY DV DD V SS CV DD GP[4](EXT_INT4)/AMUTEIN1 GP[6](EXT_INT6) CV DD VSS DV DD GP[5](EXT_INT5)/AMUTEIN0 GP[7](EXT_INT7) CLKS1/SCL1 DV DD V SS CVDD TINP1/AHCLKX0 TOUT1/AXR0[4] CV DD VSS CLKX0/ACLKX0 TINP0/AXR0[3] TOUT0/AXR0[2] CLKR0/ACLKR0 DX0/AXR0[1] FSX0/AFSX0 CV DD V SS FSR0/AFSR0 DV DD V SS DR0/AXR0[0] CLKS0/AHCLKR0 CVDD V SS FSX1 DX1/AXR0[5] CLKX1/AMUTE0 VSS CV DD CLKR1/AXR0[6] DR1/SDA1 FSR1/AXR0[7] V SS CV DD SCL0 SDA0 CV DD DVDD VSS CV DD DV DD VSS V SS CVDD CV DD V SS NOTE: All linear dimensions are in millimeters. This pad is electrically and thermally connected to the backside of the die. For the TMS320C6713B 208-Pin PowerPAD plastic quad flatpack, the external thermal pad dimensions are: 7.2 x 7.2 mm and the thermal pad is externally flush with the mold compound. 10 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
SPRS294A − OCTOBER 2005 − REVISED NOVEMBER 2005 description The TMS320C67x DSPs (including the TMS320C6713B device † ) compose the floating-point DSP generation in the TMS320C6000 DSP platform. The C6713B device is based on the high-performance, advanced very-long-instruction-word (VLIW) architecture developed by Texas Instruments (TI), making this DSP an excellent choice for multichannel and multifunction applications. Operating at 225 MHz, the C6713B delivers up to 1350 million floating-point operations per second (MFLOPS), 1800 million instructions per second (MIPS), and with dual fixed-/floating-point multipliers up to 450 million multiply-accumulate operations per second (MMACS). Operating at 300 MHz, the C6713B delivers up to 1800 million floating-point operations per second (MFLOPS), 2400 million instructions per second (MIPS), and with dual fixed-/floating-point multipliers up to 600 million multiply-accumulate operations per second (MMACS). The C6713B uses a two-level cache-based architecture and has a powerful and diverse set of peripherals. The Level 1 program cache (L1P) is a 4K-byte direct-mapped cache and the Level 1 data cache (L1D) is a 4K-byte 2-way set-associative cache. The Level 2 memory/cache (L2) consists of a 256K-byte memory space that is shared between program and data space. 64K bytes of the 256K bytes in L2 memory can be configured as mapped memory, cache, or combinations of the two. The remaining 192K bytes in L2 serves as mapped SRAM. The C6713B has a rich peripheral set that includes two Multichannel Audio Serial Ports (McASPs), two Multichannel Buffered Serial Ports (McBSPs), two Inter-Integrated Circuit (I2C) buses, one dedicated General-Purpose Input/Output (GPIO) module, two general-purpose timers, a host-port interface (HPI), and a glueless external memory interface (EMIF) capable of interfacing to SDRAM, SBSRAM, and asynchronous peripherals. The two McASP interface modules each support one transmit and one receive clock zone. Each of the McASP has eight serial data pins which can be individually allocated to any of the two zones. The serial port supports time-division multiplexing on each pin from 2 to 32 time slots. The C6713B has sufficient bandwidth to support all 16 serial data pins transmitting a 192 kHz stereo signal. Serial data in each zone may be transmitted and received on multiple serial data pins simultaneously and formatted in a multitude of variations on the Philips Inter-IC Sound (I2S) format. In addition, the McASP transmitter may be programmed to output multiple S/PDIF, IEC60958, AES-3, CP-430 encoded data channels simultaneously, with a single RAM containing the full implementation of user data and channel status fields. The McASP also provides extensive error-checking and recovery features, such as the bad clock detection circuit for each high-frequency master clock which verifies that the master clock is within a programmed frequency range. The two I2C ports on the TMS320C6713B allow the DSP to easily control peripheral devices and communicate with a host processor. In addition, the standard multichannel buffered serial port (McBSP) may be used to communicate with serial peripheral interface (SPI) mode peripheral devices. The TMS320C6713B device has two bootmodes: from the HPI or from external asynchronous ROM. For more detailed information, see the bootmode section of this data sheet. The TMS320C67x DSP generation is supported by the TI eXpressDSP set of industry benchmark development tools, including a highly optimizing C/C++ Compiler, the Code Composer Studio Integrated Development Environment (IDE), JTAG-based emulation and real-time debugging, and the DSP/BIOS kernel. TMS320C6000, eXpressDSP, Code Composer Studio, and DSP/BIOS are trademarks of Texas Instruments. † Throughout the remainder of this document, TMS320C6713B shall be referred to as C6713B or 13B. POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 11
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Page 5 and 6: GDP and ZDP 272-Ball BGA package (b
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VSS SIGNAL NAME PYP PIN NO. GDP/ ZD
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VSS SIGNAL NAME PYP PIN NO. GDP/ ZD
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EDMA module and EDMA selector (cont
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PLL and PLL controller SPRS294A −
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multichannel audio serial port (McA
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multichannel audio serial port (McA
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PARAMETER MEASUREMENT INFORMATION S
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PARAMETER MEASUREMENT INFORMATION (
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INPUT AND OUTPUT CLOCKS SPRS294 −
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INPUT AND OUTPUT CLOCKS (CONTINUED)
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ASYNCHRONOUS MEMORY TIMING (CONTINU
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SYNCHRONOUS-BURST MEMORY TIMING tim
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SYNCHRONOUS DRAM TIMING timing requ
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SYNCHRONOUS DRAM TIMING (CONTINUED)
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SYNCHRONOUS DRAM TIMING (CONTINUED)
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HOLD/HOLDA TIMING SPRS294 − OCTOB
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timing requirements for reset †
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EXTERNAL INTERRUPT TIMING SPRS294
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MULTICHANNEL AUDIO SERIAL PORT (McA
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INTER-INTEGRATED CIRCUITS (I2C) TIM
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HOST-PORT INTERFACE TIMING SPRS294
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HOST-PORT INTERFACE TIMING (CONTINU
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MULTICHANNEL BUFFERED SERIAL PORT T
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GENERAL-PURPOSE INPUT/OUTPUT (GPIO)
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MECHANICAL DATA SPRS294 − OCTOBER
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SPRS294 − OCTOBER 2005 packaging
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MECHANICAL DATA MPBG274 - MAY 2002
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IMPORTANT NOTICE Texas Instruments
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TMS320C6713B Floating-Point Digital Signal Processor (Rev. A)

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